The design of an adaptive total sliding mode control (ATSMC) system for the current control of power factor correction (PFC) is addressed in this paper. The designed ATSMC can achieve elegant performance under ideal condition as well as the existence of parameters variations, moreover, the designed controller parameter is adjusted adaptively to overcome the potential chattering. The merits of the designed ATSMC is verified by a boost type PFC prototype, the simulation and experiment results show that the PFC circuit can achieve unity power factor and sinusoidal grid current, simultaneously, the output voltage has well dynamic and steady state performance.
In this paper, the analysis and design of a wide band bandpass substrate integrated waveguide (SIW) filter are presented. A middle layer metal patch is designed in the SIW not only to create two transmission zeros due to 3D separate electric and magnetic coupling paths (SEMCP) but also miniaturize size of the filter. Since 3D electric and magnetic coupling paths are separate, the two transmission zeros above and below the passband can be independently controlled. Defected ground structure (DGS) is designed with substrate integrated waveguide not only for sharp rejection but also for its bandstop characteristics. The design is then verified by simulation and experiment.
In this paper, a one-step model extraction method is proposed for parameter identification of two-box nonlinear model of power amplifiers. In order to simplify the extraction complexity, the Wiener and Hammerstein-based serial structure is replaced by a parallel structure. The dynamic nonlinear filter curve and the static piecewise function formed by linear interpolating LUT entry are jointly curve-fitted to identify the parameters of the two-box model in one step. Compared with the traditional two-box model extraction method, the resultant data shows a comparable linearization performance of the proposed model in suppressing the adjacent channel error power with simplified procedures.
Network on Chips (NoCs) as the compromising communication infrastructures in many-core system, are suffering the serious Multi-Cell Upsets (MCU) impacts. To accelerate the accurate assessment of the increasing and complex MCU in fault tolerant NoCs, we propose a virtual filter based analytical methodology. The approach converts an original MCU model to a new regenerated MCU model via fault tolerance filtering, and then maps the new MCU information into an existing boundary model to estimate the effectiveness of fault tolerant schemes fast. The diverse results demonstrate that the virtual filter based assessment achieves 473.75× speedup and only 11.454% accuracy loss over the latest fault injection.
This study investigates noise current propagation in a power module accompanied with its switching operation. The noise current can be estimated from the measured near magnetic field. The proposed measurement system is developed to identify the time-dependent near magnetic field distribution in a power module. The system scans near magnetic field spatially and acquires its time-synchronized frequency spectrum. Propagation of the noise current in the power module is visualized as a time series of the noise current spectrum distribution in the power module. The developed system can help realize electromagnetic compatibility (EMC) design of a power module.
In this letter, a novel balanced tri-band bandpass filter (BPF) is developed by using the proposed sext-mode stepped-impedance square ring loaded resonators (SI-SRLR). The new SI-SRLR has six resonant modes, including three differential-modes (DMs) and three common modes (CMs). The operating mechanism of these resonances are explored by the even-/odd-mode method and simulation techniques. Three DMs of the proposed resonator are used to build the triple DM passbands. The appropriately admittance ratio K of SI-SRLR is chosen to inhibit the CM signal in within three DM passbands. Moreover, three T-shaped stubs are loaded to enhance the CM suppression. Finally, a balanced tri-band BPF with compact size and high selectivity is designed, fabricated, and measured. The measurements are in good agreement with the simulated results, which verifies well the proposed structure and design method.
With the extensive application of signal processing, FFT on DSP processors evoke to be the trend. Aiming at solving the conflicts in memory accessing of these applications, an address generation technique called Mod-N Address is presented this paper. This scheme avoids the influence and conflicts of accessing to one specific bank at the same time. Instead, the data accessing pressure had been shared evenly into an independence block. Furthermore, a novel conflict-free memory-addressing scheme called Modulo-Block Scheduling (MBS) is proposed to ensure the continuous operation. We prove that the solution could achieve conflict-free accessing without extra time overhead and the unit had been implemented on our platform HXDSP104x. From the results, we can see that proposed unit achieves a 1.4 speed-up compared with the previous scheme, and experimental evaluations also show that the structure outperforms by an average of 8% to 54% compared with the conventional methods in performance.
In this paper, an antenna element and array for broadband application are proposed. The original antenna element consists of a parallel-double transmission line (PDTL) fed ellipse dipole and a reflecting plate for unidirectional radiation, high-gain, and high efficiency operation. By introducing a circular patch as parasitic radiator, the voltage standing wave ratio (VSWR) ≤ 2 is achieved from 3 GHz to 9 GHz and the element shows a stable radiation pattern during the operating band. In order to reach a high gain performance, a 4 × 8 array is investigated. For the broadband performance of the proposed antenna array, a broadband and low loss tapered PDTL network is used to construct the array. Finally, to verify the feasibility of the proposed antenna, a prototype array is manufactured and measured. Experimental results are found in acceptable agreement with the simulated ones in terms of gain, radiation efficiency, radiation pattern, and VSWR. The result indicates that the proposed antenna has an impedance bandwidth (IBW) for VSWR ≤ 2 of 100% ranging from 3.0 to 9.0 GHz. Meanwhile the radiation efficiency is better than 82.7% and the gain varies from 14.8 to 20.9 dBi within the IBW.
Memristor holds great potential for memory technology, neuromorphic systems and digital applications. For implementation in complex circuits, an accurate and predictive model is required to make significant progress. This paper introduces a model that is based on the physics of the device. The mathematical modeling helps in understanding the physical properties which determine the behavior of the memristor and also aid in the characterization of the device. Namely, i-v characterization and switching mechanism involved are examined. In our SPICE modeling, Simmons tunnel barrier is incorporated into the port and state equation. The SPICE equivalent circuit for the same is presented and discussed. The presented model satisfies the fingerprints of the memristor.
This paper presents a 39 GHz broadband high-isolation mixer for 5G applications in 65 nm CMOS process. By adopting a common-gate (CG) gm stage with magnetic coupling, the mixer obtains a wide RF bandwidth without extra input matching components, which is benefit for system-level design. Meanwhile, it can improve gain and noise performance. Besides, a fully symmetrical design method is employed to keep a minimum LO leakage. According to experimental results, the mixer operates from 27.6 to 57.8 GHz and achieves a gain of 7.3 dB under LO power of 0 dBm. The LO-RF and LO-IF isolations are 59.5 and 57 dB, respectively.
A self-powered zero-quiescent-current active rectifier for piezoelectric energy harvesting is proposed. It consists of two cross-biased PMOS transistors and two active diodes. To achieve zero quiescent-current, a bias-free clamping circuit is designed to clamp the drain-source voltage of the NMOS transistor of the active diode. Post-simulation and measurement results show that the proposed active rectifier achieves an efficiency improvement of more than 40% vs. the ordinary full-bridge rectifier; the power transferred by the rectifier from the piezoelectric energy harvester (PEH) to the storage capacitor is increased significantly, especially even when the output power of PEH is low.
This paper presents a CMOS reference circuit which can work properly under the near-threshold voltage of 0.6 V. It is based on the temperature characteristic of NMOS&PMOS transistors in the sub-threshold region. The temperature curve of the NMOS quasi-PTAT current and the PMOS quasi-PTAT current can be adjusted to have the same slope factor. Thus a temperature-stable reference voltage can be achieved by subtracting the quasi-PTAT voltage generated by the NMOS and PMOS circuits. It can be used under the supply voltage of 0.6 V, under which a traditional bipolar-based band gap reference cannot work properly. The circuit is designed and implemented in SMIC 65 nm CMOS process. It provides a nominal reference voltage of 154 mV, a average temperature coefficient of 87 ppm/°C in [−10°C∼80°C] under a 0.6 V supply voltage. The total power consumption is 60 µW and the chip area is 345 um * 182 um.
The wavelength range of 1000–1260 nm, known as T-band, where T denotes “thousand”, is one of the promising wavebands suitable for the future moderate-range optical networks. We have developed T-band specific semiconductor devices based on quantum-dot technology. However, the cut-off wavelength of optical fiber cables currently utilized in access networks, i.e., G.652 fibers, is specified to be less than 1260 nm. Therefore, the fibers do not fully support the T-band. This letter presents a demonstration of the feasibility of 10-Gbit/s transmission over G.652 fibers in the T-band by experiments.