A fully integrated output capacitor, MOS-only reference, 55mnm low-dropout regulator (LDO) with optimized area and power is proposed in this letter for system-on-chip (SoC) in self-powered Internet of Things (IoT) applications. The small fully integrated output capacitor saves both area and cost, but brings challenges to the system’s stability and transient response. In order to improve system stability with optimized area, a dynamic attenuation buffer along with nested miller compensation are proposed to ensure sufficient phase margin over load range. To improve transient response with optimized power, a branch-based slew-rate enhancement (BBSRE) circuit is applied without additional quiescent current. Also, a multi-threshold MOS-only voltage reference is implemented to achieve sub-1V output and nanopower consumption with small area. The proposed LDO is fabricated in 55 nm CMOS process with the fully integrated capacitor of 5pF, occupying an area of 264µm×300µm. The quiescent current is 2µA with the figure-of-merit (FOM) of 2.
This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.
This paper presents an ultra-wideband injection-locked frequency divider (ILFD) design which is applicable to a multi-applications system. A transformer-based multi-order resonator is utilized in the ILFD to attain a flat phase response. The passive injection-boosted technique is proposed to increase the injection signal amplitude and thus widen the locking range. With the injection-boosted technique and the multi-order resonator, the proposed ILFD demonstrates a measured locking range of 50GHz, covering 48GHz to 98GHz. The divider designed in a 40-nm process consumes a DC power of 11.2mW excluding buffers and occupies a core size of 0.38×0.63mm2.
Realisation scheme of a linear voltage controlled quadrature oscillator (LVCQO) using the new second generation voltage conveyor (VCII) is proposed. The topology utilizes a pair of matched analog multiplier devices coupled appropriately with the VCII, as the active building block (ABB). The oscillation frequency (fo) is linearly tunable by the multiplier control voltage (V); experimental verification exhibits a linear tuning-range upto fo∼10MHz with measured THD∼2% with satisfactory phase-noise figure.
A new spectral testing algorithm is proposed to estimate the dynamic parameters accurately when the signal source suffers the amplitude drift. The output data of the Analog-to-Digital Converter (ADC) under test are divided into several segments. By estimating original fundamental via the Least squares method and reconstructing a non-drift fundamental to replace it, the new data are reconstructed without amplitude drift and hence the spectral leakage is removed. Extensive simulation results and algorithm analysis validate the functionality and robustness of the proposed method. The comparison with other state-of-the-art methods is also presented. The proposed algorithm relaxes the stringent requirement of the test environment, and reduces the test cost significantly.
A low voltage high-accuracy power on reset circuit with an ultra-low quiescent current is proposed in this paper. The circuit employs a 5-transistor voltage reference with a good temperature stability instead of bandgap to provide a precise reference voltage, which is compared with the supply voltage to generate an accurate trip voltage. A 4-transistor complementary-to-absolute-temperature voltage reference is proposed for temperature compensation and reduces significantly the trip voltage deviation. The proposed circuit is implemented in 55-nm CMOS process with an area of 2080µm2. The measurement results show that the trip-voltage deviation is only 5mV from -40°C to 125°C. And it achieves a power consumption of 1.76nW at 0.6V.
This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1GHz. CASSANN-v2 provides the function of on-chip SRAM memory real-time adaptive tuning by parameter configuration to reduce the intermediate output data transmission to further exploit the acceleration performance. The system simulation results show that CASSANN-v2 exhibits excellent performance on VGG-16 and ResNet-18 inference, with a throughput of 1009.54GOPS and 923.24GOPS at 1GHz, which achieved 98.59% and 90.20% average processing element utilization, respectively. Compared with state-of-the-art accelerator works, CASSANN-v2 improves the resource utilization by 2.02× in VGG-16 and 2.35× in ResNet-18.
A new circuit architecture to drive GaN e-HEMT power device was proposed in this work, which was taped out on TSMC 0.18um BCD process and successfully tested. With the proposed driver circuit, gate voltage overshoot as well as ringing on GaN e-HEMT device has been successfully suppressed, while not sacrificing GaN e-HEMT advantage of high switching speed. The proposed GaN driver realized 1.1ns rising time, 910ps falling time, and minimum 1.8ns output pulse width with almost no gate ringing and overshoot. This technology could potentially improve the system stability and reliability when driving GaN e-HEMT power devices.
An optical triode switch using phase change material (PCM) operating as a Mach-Zehnder interferometer (MZI) or as a directional coupler (DC) is proposed. The characteristics of optical triode switches are calculated by using finite-difference time-domain (FDTD) method. Ge2Sb2Te5 (GST) and Ge2Sb2Se4Te1 (GSST) are used as the PCM. In our calculation models, the signal light has a wavelength of 1550 nm, and the phase of the PCM is controlled by light with a wavelength of 1300 nm input into additional waveguides. In the MZI-type triode switch, PCM patches are laid on several crossings between the signal waveguides and the control waveguides. The DC-type triode switch consists of three parallel waveguides, and the control light is input to the center waveguide which has the PCM layer on it. The structures are optimized to have low loss and low crosstalk. In addition, the energy and pulse power required to change the phase are estimated for both types of switches.