We design a novel chaotic oscillator based on a new boundary-restricted HP memristor model. This system is mathematically simple, while dynamics rich. It is found that the system keeps chaotic within a wide range of the parameter, and the amplitude of chaotic sequences can be modified into infinite or infinitesimal by changing the parameter value of the memristor model linearly. Moreover, initial values of the width of doped region do not have influence on system’s stability. The two features give the memristor advantages in generating a large key space and adjustable chaotic signals continuously. Circuit simulation of the system which shows good agreement with numerical results is also given.
This paper focuses on the imbalance problem of serial cells in lithium-ion batteries applied in electric vehicles (EVs). In order to meet more strict requirements of size, efficiency, cost, and reliability in commercial application, a highly-integrated and efficient distributed battery balancing system is developed. In the system, each balancing node (BN) and its controller, a designed specific integrated circuit (IC), are independent, distributed and integrated in an IC-packaged module. Besides, a 50% state-of-charge (SOC)-aligned balancing strategy is proposed and applied. The experiment and commercial application results show the designed balancing system performs excellently in improving battery capacity and extending cycle life.
The parallel sampling structure of hybrid filter bank (HFB) has been considered as a promising candidate for realizing analog-to-digital conversion with high speed and high resolution simultaneously. However, the HFB design faces a challenge of accurately approximating the ideal synthesis filter frequency responses, which are discontinuous when the widely-adopted analysis filters are used. In this work, we analyze the origin of the ideal synthesis filter discontinuities. To address the discontinuity problem, we propose a novel oversampling scheme, i.e., artificially modifying the analysis filter frequency responses in the oversampling band. Performance evaluation reveals that the proposed oversampling scheme can significantly improve the HFB’s reconstruction accuracy, while avoiding the existing methods’ demerits such as the ill-conditioned coefficient matrix and the large reconstruction error in the oversampling band.
A PFC circuit for applications higher than 2 kW is generally configured by an interleaved structure, which reduces component stress and the ripple of inductor currents and output voltage. However, when implemented with GaN HEMT and controlled by a double sliding mode, a high-power totem pole PFC could achieve better performance without an interleaved structure.
An improved BIJM (Built-in jitter measurement) circuit is presented in this paper, which is consisted of three improvement points. Firstly, multi-phase sampling technology improves the sampling efficiency based on the specially designed multi-phase clock generation circuit. Secondly, the median-edge alignment is used as the new jitter extraction method, which is taking the place of the mean-edge alignment. This method can filter low-frequency noise component to extract the cycle-to-cycle jitter. Thirdly, single-edge accumulation data processing method accumulates one edge in each cycle, blocking the correlation of adjacent sampling location, which can improve measurement accuracy and save the area overhead. The proposed jitter measurement circuit is designed at SMIC 40 nm CMOS process, and the circuit occupies a total silicon area of 9108 um2. Post-layout simulation results show the measurement error is only 0.94%.
A new hybrid built-in self-test (BIST) test scheme is proposed. The test scheme consists of two components: the free LFSR mode (pseudo-random test) and the controlled LFSR mode (deterministic test). In order to improve the test quality of pseudo-random test sequence, a forward-backward pseudo-random test generation method is proposed. As every shifted-in bit is fully used to generate the most efficient test and the ratio of do not care bits is maximized in the remaining test pattern repository, the proposed controlled LFSR test generation method can find the targeted pattern with the minimal number of shift, efficiently embedding the deterministic test set into test-per-clock stream. Simulation results demonstrate that the proposed method considering for layout constraints shows great advantages in test data storage and test application time compared with previous methods.
For Flash memories, data remanence can cause differences in threshold voltage among the erased cells. By detecting such differences, already-erased data can be recovered. To decrease the differences, a secure deletion method of data is investigated in this paper. The effects of erase-erase (EE) operation and erase-program (EP) operation on threshold voltage are studied in theory. Based on the floating-gate device model, the optimal overwriting sequence, EPEPE, is obtained by simulation. This sequence can reduce the difference to 0.1 mV in threshold voltage among the erased Flash cells, which equals to that caused by one floating-gate electron.
This paper presents a low-power reference voltage buffer with fast load transient response that can be used to drive capacitive loads. The circuit is based on an improved replica-biasing source follower structure that combines the high precision of the closed loop and the high bandwidth of the open loop, and it meets the requirements of high precision, fast load transient response for a sigma-delta modulator. The proposed circuit is implemented in 0.18 µm CMOS technology provided by Semiconductor Manufacturing International Corp. (SMIC). The reference voltage buffer is combined with a sigma-delta modulator. The result shows that when the load capacitor is 10 pF, the settle time is 134 ns, the quiescent current is 81.5 µA, and the chip area is 117 µm × 220 µm.
Low-Density Parity-Check (LDPC) codes have capacity-approaching error-correction performance which makes them popular in communication system. Gradient descent bit flipping (GDBF) algorithms show an error correction capability superior to most known BF algorithms. In this paper, we propose an improved gradient descent bit flipping (IGDBF) algorithm for LDPC codes on BSC channel. Compared to GDBF algorithm, the proposed algorithm reconstructs the composition of energy function, and adds a penalty term to help it converge. Simulations show that the proposed algorithm has good performance and fast convergence rate.
Moisture sensors have been widely implemented in agricultural and forestry applications, but they can not obtain satisfied sensing performance without calibration. This letter presents an integrated moisture and temperature sensor with a model based linearization for eliminating the temperature-dependent nonlinearity. The temperature related nonlinear model is built by analyzing the relationship between the real moistures and the pairs of measured moistures and temperatures. The least squares algorithm is applied to estimate the coefficients of the obtained nonlinear model. The proposed linearization system has the advantage of wide suitability and applicability, and its performance is validated by experimental results.
An asynchronous dual-switch hybrid envelope tracking (ET) supply modulator is proposed in this paper. Two high-efficiency switching amplifiers (SA) working at different speed are adopted to reduce the current supplied by the linear amplifier (LA), which improves the efficiency of the supply modulator. A highly reliable control circuit is presented to make the SAs work asynchronously. Measured with 20 MHz LTE signal, the proposed supply modulator’s average efficiency reaches 86% when the output power is 29.7 dBm. The supply modulator is fabricated in 180 nm CMOS technology with 0.7 × 0.7 mm2 die area.
This paper proposes an energy-efficient reconfigurable architecture for deep neural networks (EERA-DNN) with hybrid bit-width and logarithmic multiplier. To speed up the computing and achieve high energy efficiency, we first propose an efficient network compression method with hybrid bit-width weights scheme, that saves the memory storage of network LeNet, AlexNet and EESEN by 7x–8x with negligible accuracy loss. Then, we propose an approximate unfolded logarithmic multiplier to process the multiplication operations efficiently. Comparing with state-of-the-art architectures EIE and Thinker, this work achieves over 1.8x and 2.7x better in energy efficiency respectively.
A novel single-stage bridgeless AC/DC power-factor-correction (PFC) converter with galvanic isolation is proposed in this paper. An auxiliary switch and a clamp capacitor are connected in parallel with primary side of the transformer to reduce the voltage stress of main and auxiliary switches. The resonant inductance and the resonant capacitor are resonant to achieve zero-voltage-switching (ZVS) for both main and auxiliary switches. The main switches share the same driver signal, and the converter does not need to sense the positive or negative ac input voltage, so it could be easily implemented with available average current model control IC. The detailed ZVS operation principle of the system is presented. The proposed converter has the advantages of minimum component count, galvanic isolation and higher efficiency. Simulation and experimental results are presented for a 3000 W prototype circuit at 85 kHz switching frequency to demonstrate the effectiveness of the proposed converter.
A broadband bandpass filter with a dual-plane structure is proposed. The dual-plane structure consists of a pair of L shaped microstrip feed lines on the top layer and a triple-mode defected ground structure resonator (TMDGSR) on the bottom layer. Electric field distributions and frequency response of the TMDGSR are investigated. A sample filter using TMDGSR with a 31.9% of 3-dB relative bandwidth at the centre frequency of 3.6 GHz is fabricated and measured. The simulation and measurement results show that the TMDGSR has some advantages such as: simple compact triple-mode resonator structure and broadside coupling with feed lines easily, which are very useful in broadband DGS BPFs design.
Electrical contact failures may alter the signals that are being transmitted and is one of the major causes of system failure. In this letter, an equivalent model of the connector with a degraded contact surface is developed and its transmission characteristics are analyzed. The effects of electrical contact degradation on high-speed digital signal transmission are studied. And the experimental results verify the theoretical analysis. The results of this letter are helpful in developing a better understanding of high-speed connection devices, and provide a theoretical support to identify failure features in fault diagnosis.
Thermal characterization and modeling of power module is inevitable to take full advantages of power semiconductor device. Dynamic thermal modeling of power module, which is related to packaging structure and material property, is attracted attention for power electronics system design. The transient thermal resistance measurement standard, called static test method (JESD51-14 ), utilizes temperature dependency in I − V characteristics of power semiconductor device to estimate junction temperature. The dynamic gate threshold voltage shift of SiC MOSFET violates junction temperature estimation. This paper proposes accurate transient junction temperature estimation procedure for SiC MOSFET with advancing the static test method, and validates the temperature estimation with temperature sense diode embedded in SiC MOSFET. The proposed procedure enables to get accurate time response of TJ for SiC MOSFET, which enables dynamic thermal modeling of power module with SiC MOSFET.
A pre-distortion linearized Darlington cascode power amplifier cell is explored for broadband amplifier implementation, with additional inclusion of a RLC peaking network at the base terminal of the cascode transistor, and a RC feedback network at the input Darlington transistor. The RLC peaking network optimizes bandwidth and large signal power gain. The RC feedback network simplifies the design of broadband matching for the input Darlington pair. Most importantly, an optimization method of the input Darlington transistor biased at saturation mode is proposed to function as a predistortion linearizer, which can compensate for gain compression and phase deviation effects of the following cascode power stage. With this compensation technique, the proposed broadband PA operating over a frequency range from 0.2 to 6 GHz achieves higher OIP3 than the conventional Darlington cascode amplifier, resulting in a 5 dB improvement of OIP3 at 6 GHz. A P1 dB ranging from 24 to 27 dBm over the frequency range is achieved by this broadband power amplifier with a 0.27 mm2 InGaP/GaAs HBT chip die.
The WK-recursive network well conforms to implementation of large distributed systems due to its many favorable properties. In this paper, we employ the concept S3 group to establish an efficient look-ahead routing algorithm for the triplet-based WK-recursive network. Remarkably, we introduce a data flow model to categorize message traffic as six flow models. For the sake of simplicity, we further leverage the permutation group S3 to transform different flow models to one model and hence routing computing can be performed in the same model. It is demonstrated that our proposed design can achieve better network performance.