IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 12 , Issue 16
Showing 1-9 articles out of 9 articles from the selected issue
LETTER
  • Zheng Lu, Chao Li, Chao Chen, Guangyou Fang
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 16 Pages 20150446
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 21, 2015
    JOURNALS FREE ACCESS
    Pre-distortion approach is used in frequency synthesizers to compensate the statistical phase errors in the synthesized signal. However, as the systems becoming more and more complex, it is hard to describe the phase errors for a complex system with one single model. In this paper, a hybrid pre-distortion approach was proposed for a transmitter composed of different modules with high frequency modulation rate. Models for different modules are combined to form the hybrid distortion model. Based on the proposed model and the convenience of the Direct Digital Waveform Synthesis (DDWS) technology employed in the transmitter, the distortion of a complex system can be feasibly compensated. Experimental studies were performed with reduced phase errors and improved range profiles achieved, which verify the effectiveness of the proposed approach.
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  • Shuja Ahmad Abbasi, Zulhelmi, Abdul Rahman M. Alamoud
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 16 Pages 20150450
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 21, 2015
    JOURNALS FREE ACCESS
    This research is about a new approach, which is used for optimizing multipliers designs, which are based on the concept of Vedic mathematics. The design has been targeted to to FPGAs (state-of-the art field-programmable gate arrays). It has been assessed that the multiplier produces partial products by utilizing Vedic mathematics concept by deploying basic 4 × 4 multipliers, which is designed by exploiting special features of multiplexers and 6-input look up tables (LUTs) on the same slices, resulting in considerable minimization in area. The multiplier has been realized on Xilinx® Virtex-5 FPGAs. It is significant to notice that pipeline adders were used to obtain final products. Furthermore, the multiplier is developed and organized by using pipeline schemes, which contribute to the enhancement of operating frequency of the multiplier. The results show that the 32-bit pipeline multiplier can work up to a clock frequency of 450 MHz. It has utilized 514 slices and 1157 flip-flops and has much less dynamic power than the other reported work.
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  • Jiajia Jiao, Xing Han, Yuzhuo Fu
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 16 Pages 20150453
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 31, 2015
    JOURNALS FREE ACCESS
    With scaling technology node, soft error has dominated in the integrated circuit failure. To tradeoff the design cost and reliability, efficient reliability analysis methods are required to select the appropriate reliable schemes. In this paper, we propose a multi-level Probabilistic Graphical Models (PGM) based method for the soft error analysis of data Cache structure. The proposed method includes two points: 1) Exacting the error masking dependencies from the ALU instruction execution procedure, and calculating the first-level masking rate between ALU and register file; 2) Drawing the error spreading dependencies graph from the load and store instruction processing, and computing the higher-level masking rate between ALU and Data Cache. The simulation results of SPEC2K demonstrate that, compared with the existing methods, the proposed method achieve up to 16.19% accuracy improvement and 52.72× speedup.
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  • Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 16 Pages 20150489
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 27, 2015
    JOURNALS FREE ACCESS
    3D ICs is a solution for multi-core processors, with critical challenge of internal thermal problem. A new solution for this problem is interlayer cooling system, which expands the floorplan design space of micro-processors in 3D ICs. This work proposes a floorplanner for multi-core processor in 3D ICs with interlayer cooling system, integrated with greedy and particle swarm optimization method. The results show that the maximal temperature and temperature gradient reduced by 10.3°C and 9.2°C respectively, compared with the baseline design in 3 active device layers.
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  • Seongsoo Lee, Yongju Jang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 16 Pages 20150529
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 27, 2015
    JOURNALS FREE ACCESS
    A battery lifetime and PSNR quality-scalable video transmission is proposed. Video bitstream is intentionally encoded at lowered bitrate, and it is intermittently transmitted to exploit battery recovery effect. Battery lifetime is extended significantly with PSNR quality degradation given by user. Both battery lifetime and PSNR quality are precisely estimated and easily controlled by adjusting encoding bitrate and battery duty ratio. Battery lifetime extension is fully scalable with PSNR quality degradation, and vice versa. Measured battery lifetime was extended up to 31.4 times at the cost of 1.20∼3.89 dB PSNR degradation in H.264 video coding and ZigBee transceiver. Absolute average errors of estimated PSNR degradation and battery lifetime were less than 7.31%.
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  • Tong-Feng Zhang, Shou-Liang Li, Rong-Jun Ge, Min Yuan, Guan Gui, Yi-De ...
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 16 Pages 20150530
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 31, 2015
    JOURNALS FREE ACCESS
    A novel chaotic pulse sequence generator is presented, which includes a tent map function subcircuit and an iterative operation subcircuit. Fewer components are utilized to implement the tent map function subcircuit. Based upon boundedness of the tent map series, the iterative operation is automatically implemented through reasonable design without clock control. The method we adopt can contribute to realize the tent map as well as yield chaotic pulse train, which is controllable in terms of pulse position and pulse time interval. The results from both the test circuit and numerical simulation verify the validity of our design.
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  • Yu Guo, Shanwen Hu, Xiaozhou Liu, Haodong Wu, Guojun Wang, Guann-Pyng ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 16 Pages 20150576
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 31, 2015
    JOURNALS FREE ACCESS
    A novel compact customizable EBG (Electromagnetic Bandgap) filter operating from 2.6 to 10.0 GHz is proposed. The EBG filter is manufactured by a 2-layer PCB (Printed Circuit Board) process in RO4350 substrate with surface mounted lumped capacitors. A specific working frequency of the filter is selected on demand by adjusting the value of the capacitors, while the filter’s performance is not compromised. The experimental results show a filter with size of 2.50 × 3.00 × 1.00 mm3 in PCB achieving performance of insertion loss of 3.34 dB, 1.19 dB and 1.20 dB at 2.60 GHz, 7.71 GHz and 10.0 GHz with the capacitor of 5.1 pF, 0.5 pF and 0.3 pF respectively.
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  • Wuhuang Huang, Houjun Wang, Peng Ye, Kuojun Yang, Jun Jiang, Huiqin Pa ...
    Type: LETTER
    Subject area: Electronic instrumentation and control
    2015 Volume 12 Issue 16 Pages 20150585
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: July 27, 2015
    JOURNALS FREE ACCESS
    Multiple-converter synchronization (MCS) is essential for the reliability of ultra-fast time-interleaved analog-to-digital conversion (UF-TIADC) systems or instruments. In this paper, a novel and versatile solution based on phase-sifting approach is proposed in detail for generalized systems. And then, the instantiation design and test are carried out in a 20GSPS TIADC system consisted of four universal 5GSPS ADCs. The results show that the proposed solution is effective on solving the MCS issue and provides a solid timing foundation for further data processing in UF-TIADC systems. Moreover, it offers a practical reference for the MCS implementation of higher-speed sampling systems or instruments.
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  • Zhang Xian, Liu Hhua, Li Lei
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 16 Pages 20150597
    Published: 2015
    Released: August 25, 2015
    [Advance publication] Released: August 07, 2015
    JOURNALS FREE ACCESS
    A low jitter phase-locked loop (PLL) based on self-biased techniques was designed. The PLL achieves process independent and low input tracking jitter. A novel cascode charge pump (CP) is realized to improve the current matching so as to reduce the jitter of the system. A capacitor is employed in the second CP to make third order PLL. The PLL is fabricated in SMIC 0.13 µm CMOS process, which achieves a very wide tuning range from 625 MHz to 1.5 GHz. And the phase noise of the VCO at 1 MHz offset from the 1.25 GHz only has −94.66 dBc/Hz. The measured RMS jitter and peak-to-peak jitter at 1.25 GHz only have 3.53 ps and 21.19 ps.
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