IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 16
Showing 1-7 articles out of 7 articles from the selected issue
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LETTER
  • Tao Chen, Xiaohong Sun, Jianhui Wu, Xu Niu, Huai Gao
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 16 Pages 20130470
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: August 01, 2013
    JOURNALS FREE ACCESS
    A stacked power amplifier (PA) using 2-µm GaAs HBT process is presented for 2.4GHz application. The stacked configuration can increase the output power by raising the supply voltage of the circuit. Additionally, a novel inter-stage matching technique with series RC is proposed to suppress the efficiency degradation caused by the parasitic capacitance. The measurement results show the compensation technique improves PAE by more than 6%, while the error vector magnitude (EVM) is enhanced. And the fabricated PA shows a gain of 23.7dB and a saturated output power of 32dBm with PAE of 50%, while the EVMs are lower than 3% up to 26dBm of OFDM/64QAM output power.
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  • Hyeonho Song, Jintae Kim, Minjae Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 16 Pages 20130482
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: July 23, 2013
    JOURNALS FREE ACCESS
    A low power reference buffer is proposed to achieve high PSRR and less crosstalk between channels for time-interleaved analog-to-digital converters (ADCs). A conventional approach requires enough bandwidth in feedback amplifiers to suppress high frequency supply noise, which tends to increase power consumption. Furthermore the number of output drivers that share error amplifier output is unavoidably limited due to the coupling across ADC channels. We propose design techniques to improve the corner frequency of power supply rejection ratio (PSRR) by a factor of 100 and the cross-channel isolation by 20dB without drawing more current.
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  • Li Zhou, Hengzhu Liu, Jianfeng Zhang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 16 Pages 20130506
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: July 25, 2013
    JOURNALS FREE ACCESS
    This paper presents a cluster-based coarse grained reconfigurable array (CGRA) architecture and a corresponding modulo scheduling method for the inner-most loop. The reconfigurable clusters in this CGRA are composed of generic processing elements (PE) and shared PEs. The local connectivity of a cluster is utilized in the proposed mapping heuristic. Routing in the PE array is avoided because data transmission is within a cluster or between adjacent clusters in the heuristic. Experiment shows that the architecture and method outperform other modulo scheduling algorithms on CGRA. Better execution delay and resource utilization ratio can be achieved at 9.8%.
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  • Hsiao-Yun Li, Shiu-Cheng Chen, Hai-Ping Chen, Wei-Cheng Ran, Jia-Shian ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 16 Pages 20130521
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: August 01, 2013
    JOURNALS FREE ACCESS
    A frequency-reconfigurable antenna based on periodically loading ferroelectric MIM capacitors along a slot loop is designed, fabricated, and measured. The antenna is fabricated on a 430-µm-thick sapphire substrate with a total area of 1×1cm2. The size of the slot loop is 2.5×2.5mm2. By changing the bias voltage of the ferroelectric varactors from 0V to 7V, the resonant frequency of the varactor-loaded antenna can be tuned from 5.57GHz to 7.33GHz, corresponding to a tuning range of 27.3%, while keeping the return loss greater than 10dB. At 5.57GHz, the size of the slot loop is 0.046×0.046λ02. When biased at 7V, the antenna gain is −10.8 dBi at 7.35GHz. Under 0-V bias, the Pin,1dB of the tunable antenna is 18.8dBm at 5.6GHz.
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  • Hong-Yeol Lim, Gi-Ho Park
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 16 Pages 20130523
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: August 07, 2013
    JOURNALS FREE ACCESS
    Three-dimensional integration circuits (3-D ICs) technology provides various opportunities for new computer system architectures. Data prefetching, which can utilize the abundant memory bandwidth of 3-D IC technology is one of the most promising approaches in 3D IC technology today. This paper analyzes the efficiency of aggressive prefetching based on the huge bandwidth of 3-D IC technology. The performance analysis results reveal that these simple aggressive prefetching mechanisms cannot achieve performance improvements even with the enormous memory bandwidth of 3-D IC technology. An adaptive L2 cache prefetching mechanism is proposed, which adjusts the amount of prefetching data adaptively based on the memory access pattern to exploit the abundant memory bandwidth effectively. The proposed mechanism can achieve a performance improvement of about 5% more on average than a conventional 1MB L2 cache, and it can significantly reduce energy consumption of an L2 cache by about 29% on average over the conventional 2MB L2.
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  • Shinpei Ogawa, Takeshi Yuasa, Yoshio Fujii, Yukihiro Tahara, Hiroshi F ...
    Type: LETTER
    Subject area: Micro- or nano-electromechanical systems
    2013 Volume 10 Issue 16 Pages 20130565
    Published: August 25, 2013
    Released: August 25, 2013
    [Advance publication] Released: August 01, 2013
    JOURNALS FREE ACCESS
    We designed and fabricated a low-loss transmission line structure with through-silicon vias (TSVs) for use in the millimeter-wave region for three-dimensional packaging of radio frequency microelectromechanical system devices. High-frequency simulations were used to determine the optimum transmission line structure. A transformer was employed to compensate for the impedance mismatch between the TSVs and the coplanar waveguide. The proposed structure was fabricated using a combination of surface micromachining and the molten solder ejection method. The electrical properties of the TSVs and the transmission line were measured, and a low insertion loss of 0.7dB at 80GHz was achieved.
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