IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 6 , Issue 9
Showing 1-10 articles out of 10 articles from the selected issue
LETTER
  • Kyu-Yeul Wang, Byung-Soo Kim, Chong-Ho Lee, Jaehyun Park, Duck-Jin Chu ...
    2009 Volume 6 Issue 9 Pages 529-534
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    We propose a CVD (Cardiovascular disease) level prediction processor which has reduced computational efforts and time with insignificant diminution of CVD diagnosis accuracy when compared to the conventional CVD level prediction methods. The proposed DNA computing algorithm for implementation of CVD level prediction processor uses masks for simple nonspecific hybridization. Using the proposed mask, we can reduce HW computational efforts. Besides this, we decrease processing time resulting by co-processing hybridizations with a number of parallel matching units. The proposed CVD level prediction processor diagnoses CVD data of patients within 3.4 us. Therefore, the proposed CVD level prediction processor can be applied in a CVD level diagnosis system.
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  • Yongseok Jin, Jinsung Kim, Hyuk-Jae Lee
    2009 Volume 6 Issue 9 Pages 535-539
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    Dynamic backlight scaling (DBS), a technique for LCD power reduction, often deteriorates image quality because of a flicker (unintended temporal variation of the luminance) generated in the frame at which the backlight level changes. This paper proposes a novel DBS algorithm to reduce the flicker by decreasing the quantization errors (QEs) that are created in the multiplication of the input gray level and the DBS scaling ratio as well as in the mapping of the multiplication result to an integer gray level. The proposed DBS algorithm reduces the QE down to 28.8% when compared with the conventional DBS algorithm.
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  • Sang-Ki Kim, Kar-Ann Toh, Sangyoun Lee
    2009 Volume 6 Issue 9 Pages 540-545
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    Due to the inherent nature of kernel implementation, the kernel Fisher discriminant suffers from the small sample size problem. In this paper, we introduce a novel variant of the kernel Fisher discriminant formulation to circumvent this problem. By adopting a two-fold regularization scheme on the scatter matrices, we show both effectiveness and reliability of the proposed method particularly regarding the small sample size and the lack of dimensionality issues.
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  • Peiman Keshavarzian, Keivan Navi
    2009 Volume 6 Issue 9 Pages 546-552
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    For the last couple of decades, multiple-valued logic (MVL) such as ternary logic styles has attracted considerable attention. MVL circuits can reduce the number of operations necessary to implement a particular mathematical function and further have an advantage in terms of reduced area. Carbon nanotube field effect transistors (CNFETs) are being extensively studied as possible successors to Silicon MOSFETs. Implementable CNTFET circuits have operational characteristics to approach the advantage of using MVL in voltage mode. In this paper through using “carbon nanotube field effect transistor” characteristics we present efficient galois field operations. Consequently, the simulation denouements demonstrate the efficient circuit parameters such as chip area, delay, power and power delay product.
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  • Keivan Navi, Mehrdad Maeen, Omid Hashemipour
    2009 Volume 6 Issue 9 Pages 553-559
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    This paper presents an area efficient, high-speed and ultra low power 1-bit full adder that uses only 9 transistors. It works based on majority function and MOS capacitors. Because of the simple structure of the proposed design and reduced transistor counts, a very low power full adder is realized. It also can work more reliably at ultra low supply voltage in comparison with the previous designs. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The adder cell is compared to four standard adders based on power consumption, speed and power delay product. Intensive simulation runs on HSPICE shows that the new adder has more than 44% in power savings over conventional CMOS adder and is 10% faster.
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  • Min Zeng, Jeong-Gun Lee, Goang-Seog Choi, Jeong-A Lee
    2009 Volume 6 Issue 9 Pages 560-565
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    This paper presents a novel two-tier low power electrocardiogram (ECG) monitoring system which consists of a sensor nodes layer and a base station layer by employing a simple but effective Euclidean distance model. To save transmission power, a sensor node only transmits sensed data to a base station when the sensed data shows abnormality. For the low power implementation of the abnormality detection on a local power-hungry sensor node, we propose light-weight computation of Euclidean distance between a sensed ECG signal and a reference ECG signal. Experimental results show that the proposed scheme can reduce power consumption by 39-57% of the sensor nodes and accordingly prolongs the lifetime of the whole monitoring system.
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  • M. Rakib Uddin, J. S. Cho, Y. H. Won
    2009 Volume 6 Issue 9 Pages 566-571
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    We demonstrate an all-optical wavelength converter with multicasting at 4× 10Gbits/s up and down conversion using gain modulation in an FP-LD. We also explain the gain modulation technique using the bistability behavior of the injection locked FP-LD. The wavelength converter shows the average power penalty of 1.5dB at a bit error rate of 10-9 and the extinction ratio of outputs over 12dB, both for up and down conversions.
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  • Jun-Seok Lim
    2009 Volume 6 Issue 9 Pages 572-578
    Published: 2009
    Released: May 10, 2009
    JOURNALS FREE ACCESS
    The problem of FIR filtering with noisy input and output data can be solved by a total least squares (TLS) estimation. The performance of the TLS estimation is very sensitive to the ratio between the variances of the input and output noises. In this paper, we propose an iterative convex combination algorithm between TLS and least squares (LS). We combine two typical iterative algorithms, the total least mean square method (TLMS) and the least mean square method (LMS). TLMS is a typical iterative algorithm for TLS and LMS is a typical one for LS. This combined algorithm shows robustness against the noise variance ratio. Consequently, the practical workability of the TLS method with noisy data has been significantly broadened.
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