This paper presents a radiation-hardened flip-flop called MSIFF. The sensitive node-pairs between the master and slave latches are readjusted at layout-level. It obtains a high SEU tolerance with slight area and performance degradation. A test chip was irradiated with the static and dynamic test modes to validate the SEU tolerance of the proposed MSIFF. Experimental results demonstrate superior performance of the MSIFF over the conventional DICE and D flip-flop.

In this paper, a novel design scheme of X-band phased array antenna is introduced. The antenna array is mainly composed of the 3D T/R module, which is based on LTCC technology, and the slotted waveguide antenna. The whole system adopts the vertical interconnected three-dimensional multi-layer technology for the spaceborne synthetic aperture radar (SAR) system. 3D T/R module greatly improves the integration of the system by assembling different multifunctional chips into a complete multi-layer LTCC substrate. The slotted waveguide antenna is connected vertically with the T/R module, the power divider, etc, implementing the integrated design. The test results of the antenna system show that the phased array antenna has a good performance in terms of gain, radiating patterns and so on, which provides a new idea for the integrated design of the phased array antenna.

This work proposes an experiment-based characterization and modeling approach for interconnection channels including via stacks as vertical transitions. A daisy chain structure implemented in a 0.18 µm RFCMOS process is used for developing and verifying the validity of the proposal. The usefulness of the models is shown by assessing the impact of the vias in a practical resonant rotary traveling wave oscillator (RTWO). The oscillation frequency of the RTWO is reduced 13.7% when the via stack models are included.

We investigate the application of convolutional neural networks (CNNs) to accelerate quantum mechanical transport simulations (based on the nonequilibrium Green’s function (NEGF) method) of double-gate MOSFETS. In particular, given a potential distribution as input data, we implement the convolutional autoencoder to train and predict the carrier density and local quantum capacitance distributions. The results indicate that the use of a single trained CNN model in the NEGF self-consistent calculation along with Poisson’s equation produces accurate potentials for a wide range of the gate lengths, and all within a significantly shorter computational time than the conventional NEGF calculations.

This paper presents a mmW quadrature down-conversion mixer for 76–81 GHz automotive radar applications. A transformer-based g_m-boosting method and a new cascode inter-stage network are proposed to improve the gain of preamplifier. A pair of cross-coupled transistors are exploited to bleed dynamic current into mixer core to reduce noise figure while utilizing its negative resistance to improve conversion gain. The mixer is implemented in a 55-nm CMOS process and the measurement results show that the BW_−3dB is 5.5 GHz, the peak gain is 4.1 dB with <0.16 dB I/Q mismatch, the input P1dB is up to −6 dBm and the minimum noise figure (NF_min) is 19 dB while dissipating 40 mW of power. The achieved FOM is up to 0.02.

This paper proposes a 55-nm CMOS analog baseband (ABB) with wide tunable bandwidth (BW) and large tunable gain, which consists of a variable-gain amplifier (VGA) and a low-pass filter (LPF) for multi-standard 60 GHz applications. A modified dual-feedback Cherry-Hooper-based VGA achieves a large gain range of −15∼73 dB. Through the analog and switched-capacitor (SC) tuning, the 8^th-order G_m-C-based LPF features a widely and continuously tunable bandwidth of 100∼1200 MHz. A linear 8-bit digital-to-analog converter (DAC) is integrated for bandwidth and gain tuning. Measurement results show that the output linearity (OP1dB) is −35.5∼3.8 dBm, and the noise figure (NF) is less than 21 dB when the gain is 56 dB while consuming 12 mW of power.

The Optical path length of an input/output optical waveguide in a Si ring filter is reduced to shorten the feedback loop length of an optical negative feedback laser. Thanks to the increase in phase margin in the optical negative feedback system, the spectral linewidth of a single-mode semiconductor laser can be reduced to 99.8 kHz.

An improved adaptive-on-time (IAOT) controlled current mode buck converter with RC-based current-sensing circuit and internal soft-start property is presented in this paper. First, the inductor current is sensed by a resistor-capacitor (RC) network, which can fully sense the trend of inductor current with high accuracy. Second, an IAOT control circuit is used to realize the on-time of the power switch adaptively changing with the operation conditions. In addition, the overshoot (undershoot) voltages are reduced by making T_ON adaptively shorter (longer) during the unloading (loading) transient due to the IAOT control. Third, soft start operation protects the circuit from large in-rush current during startup of the converter. Fourth, the proposed buck converter was implemented with standard 0.18-µm CMOS process. Simulation outcomes have shown an input voltage of 5 V, when the output voltage is ranging from 1.2 V to 3.6 V, with a maximum conversion efficiency of 98% (heavy loads) and 94% (light loads), making the buck converter quite useful in power management ICs.

In-Memory Computing (IMC) architectures based on Static Random Access Memory (SRAM) can improve system performance and energy-efficiency dramatically. However, most of the existing SRAM-based implementations are designed for specific purposes like accelerating neural networks, which limits the application scenarios of IMC. In this paper, we propose DM-IMCA, a novel IMC architecture with two work modes for general purpose processing. It utilizes our proposed 9T bitcell based computational SRAM as the location to perform IMC operations. Besides, a new IMC Instruction Set Architecture (ISA) as well as an automated vector computing mechanism are also proposed to facilitate DM-IMCA’s programming and accelerate in-memory computing, respectively. The simulation results show that DM-IMCA can bring a performance increase by up to 257x, and SRAM energy saving by up to 3x, compared to a baseline system.