In this paper, we analyze that the best mode for intra-prediction can be changed by the RD cost related with the bit to signal the prediction mode according to whether the most probable mode (MPM) and the prediction mode are same or not. With this understanding, we propose a fast 4 × 4 intra-prediction based on the MPM in the H.264/AVC. This algorithm uses a defined RD cost including the minimum bit to signal the prediction modes excluded the MPM as a threshold. Experimental results show that the proposed algorithm is capable of reducing the overall encoding time by 36% and the overall intra-prediction time by 47% compared to the full search, with negligible loss of quality.
In this paper, we propose a new dynamic power management (DPM) system based on fuzzy decision support system. Different dynamic power management policies may be implemented in the system. Based on the system requirements for each application class, one of the policies may be selected automatically. The approach, which is not dependent on the system under management, can be utilized in different systems. To show the efficacy of the fuzzy decision support system, we have compared its performance with fixed DPM policy systems. The results show that considerable improvements may be achieved in this approach compared to those systems with one DPM policy.
We propose an optical broadcast-and-select network architecture with centralized multi-carrier light source (C-MCLS). It enables all network nodes access a large number of optical carriers in a cost-effective manner through dynamic optical broadcast and select. Cost analysis and numerical results show that it greatly reduces the light source cost compared with the conventional one, as the number of required access wavelengths at network nodes becomes large. We also show its cost-effective areas in different cases of cost calculation. The obtained results indicate that it is very promising for future regional/metro networks, which demand a large number of wavelengths.
The traditional pipelined RISC processors have been the mainstream technology in high-end embedded systems; it is due to that embedded applications are often satisfied with minimum performance requirement. However, the upcoming application domain of embedded systems will require more advanced microprocessor cores due to the future computing demands. Therefore, the system would eventually have to turn to advanced processors such as superscalars for the embedded processing cores. A drawback is that the conventional design of the superscalar processors possesses inherent complexity and power problems which are not easily acceptable in the domain of embedded processors. In this paper, we investigate the possibility to use multi-threaded processors to solve the problems with the traditional superscalar processors in embedded systems.
A new approach of H.264/AVC deblocking filter based on motion activity in video sequences is proposed. Based on sum of motion vectors the thresholds have been set through experimentation for categorizing different sequences. In this approach, a modified deblocking filter is used for low to moderate motion video sequences. Various simulations are conducted to evaluate the candidacy of the anticipated technique. The subjective and objective results are in conformity of the original H.264/AVC deblocking filter for low and moderate motion video sequences. A significant reduction in average number of operations is achieved without losing quality of the video.
This paper addresses channel estimation technique with SNR measurements for low SNRs. The LS estimator is simple and adequate for high SNRs, but the LMMSE estimator of assuming a priori knowledge of SNR value and channel covariance has a better gain over LS estimator for low SNRs. In this paper we propose an SNR measurement method with a little complexity by using minimum accumulated distance in Viterbi decoder. The measured SNR value is used in the LMMSE estimator and the performance is presented both in terms of mean square error and bit error rate compared to the LS estimator and the perfect channel state information case.
In this paper, a new signaling scheme is proposed for intra-panel interface using three transmission lines for flat panel displays. The interface utilizes multi-level current signaling with delta-y configured resistor network. It increases the number of symbols and differentiates the symbols with pseudo differential signaling. The interface utilizes input buffer with low input impedance to reduce driving current. Therefore, the interface has lower frequency with low driving current when it has same data rate as conventional intra-panel interface. As a result, electromagnetic interference can be lowered. The interface is fabricated using a 0.18um CMOS technology, and its measured bit error rate was 3.9 × 10-11.
This paper proposes an efficient video stream switching scheme among compressed video streams coded at different quality levels and bit rates. The conventional stream switching scheme in H2.64/AVC is effective in switching, but degrades the compression efficiency of the transmitted stream even if the switching operation does not take place. In the proposed scheme, no modification is made to the original compressed streams so the compression efficiency is maintained at switching points. Consequently switching points can be assigned flexibly in our efficient scheme without noticeable bit rate overhead. It is shown by experimental results that the proposed scheme outperforms the conventional switching scheme.
The on-chip cache is a significant source of the energy consumption of today's processors. Several data compression techniques including Frequent Value Caches are proposed to reduce the energy consumption in the data cache memories. However, the preceding approach has some problems, such as the monitoring time to find the frequent values dedicated for each program and the additional registers to store the frequent values. By studying the behavior of MiBench and MediaBench programs, we observed that many data values stored in the data cache have a few word patterns in which one byte is repeated and/or the rest of bytes are all zeros. These values can be represented with one byte and the pattern type bits. We propose a new energy-efficient data cache, the Byte-Repeat Pattern Cache, which employs this encoding scheme.
This paper reports the principle of an micro-machined gyroscope (angular rate sensor), whose output signal is fuse both roll rate and yaw rate two information. The output sine wave frequency is the rotating carrier roll rate, which is easily detected, but the amplitude depends on the roll rate and yaw rate. Otherwise, fabrication defects are always inevitably present, which gives rise to the scale factor of different gyroscope can not be identical. In order to solve these problems, a simple method is presented. The results show that the relationship between output signals and yaw rate is linearity and thus reduce the effect of the roll rate variety on the output signal. Further, different gyroscopes have the same scale factor.