This paper presents a continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock attenuation. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in 0.18-µm CMOS technology. Simulation results summarize that eye-width of minimum 0.75UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is 3.42mW per channel, a very low value in comparison to those of previous researches, and the effective area is 0.127mm2.
A communication network for use in feedback control must satisfy strict requirements on the reliable and deterministic behavior. However, wireless sensor networks such as ZigBee may introduce randomly varying delays into the system, resulting in the performance degradation or even the instability. In this paper we propose a deterministic wireless network that can be used for feedback control. The proposed approach is based on a time-triggered mechanism implemented on top of the IEEE802.15.4 standard. The effectiveness of the proposed method is demonstrated through a set of experiments on feedback control of a DC motor.
In the paper, a transformation method of frequency filters using Balanced Output Transconductance Amplifiers (BOTA) into equivalent filtering structures with Universal Current Conveyors (UCC) is shown. A newly designed multifunction filter using two BOTAs was derived from the general autonomous circuit and transformed into a UCC-based frequency filter. The properties of the proposed second-order multifunction filter were subjected to an AC analysis in the OrCAD software and the BOTA-based circuit to experimental measurement.
This paper investigates what kinds of choices exist in determining the voting structure for cascaded triple modular redundant (TMR) modules, how to identify efficient voting structures, and the effects of voting structures on the overall system reliability. While the classic single-voter and three-voter architectures have been used for about fifty years, the paper shows that there are more practically useful voting structures which provide efficient trade-offs between hardware overhead and system reliability. Specifically, a single-voter architecture with the voter fanout of one is found to be more reliable than the classic single-voter architecture for a reasonably wide range of component reliability.
A new approach to arbitrary scaling of high quality images is proposed, whereby a 2-D M-channel DFT filter bank is designed along with its synthesis part being modified on the basis of a compactly supported sampling function. For that purpose, the 2-D down/up-sampling formulae in a closed form are derived and utilized. Also, an optimized adaptive interpolation technique is employed to compensate for quality degradation arising in scaled images. Finally, simulation results demonstrate that high quality images of arbitrary size can be obtained from the original image.
A novel programmable frequency divider in 0.18-µm standard CMOS process is presented in this paper. With less cascode CMOS-stages, the proposed design achieves a higher operating frequency compared to that of the similar programmable frequency dividers reported in the literature. Test results demonstrate that the divider can operate up to 4.5GHz. Elimination of passive resistors in the proposed scheme provides an area efficient design approach. Design improvements to achieve 50% duty cycle are also presented. Due to the lower operating frequency of the 50% duty cycle correction unit, it only adds a very small amount of power consumption penalty (∼ 10%) to the entire system.
In this paper, different structures for an elliptic filter with fixed-point arithmetic are implemented and compared. The filter must be quantized for hardware implementation. This quantization is done in two steps. First the coefficients of the filter are quantized and then the minimum required accuracy of the internal nodes is determined. According to the simulation results, lattice and DFII-parallel structures have minimal sensitivity to coefficient quantization. Also, the chip areas (i.e. gate counts)of different structures are computed. We show that overall, the DFI-parallel structure is the optimal structure for hardware implementation and requires minimal chip area at the needed precision.
We propose a new approach for tracking circular traffic signs from image sequences to improve the performance of traffic sign detection, by reducing search region and suppressing misdetection caused by temporal occlusion or poor quality of image. Our proposed tracking, called two-layered blobs tracking, does not require an accurate model of the fixed object-moving camera system, which is essential in the Kalman-Filter tracking. The experimental results show that the proposed approach could track the circular traffic signs from a moving camera effectively, without any restrictions on speed and movement of the vehicle, and camera installation, thus it is easy to be implemented in real situation.