IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 17 , Issue 20
Showing 1-4 articles out of 4 articles from the selected issue
LETTER
  • Gengxin Liu, Manqing Hu, Yitian Zhang, E Du, Dekang Liu
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 20 Pages 20200273
    Published: October 25, 2020
    Released: October 25, 2020
    [Advance publication] Released: October 06, 2020
    JOURNAL FREE ACCESS

    Non-ideal effects of ReRAM are the major limitations of deploying crossbar based neural network accelerator in the real world. Noise injection could effectively mitigate the non-ideal effects because it is equivalent to an adaptive regularization to the neural network. However, software-based noise injection involves computation-hungry retraining and data extraction. In this paper, we propose a ReRAM crossbar based neural network accelerator with current injection to adapt non-ideal effects in the ReRAM crossbar. We inject current into the crossbar through randomly set ReRAM cells to add the adaptive regularization, and no retraining and data extraction is needed in our proposal. We evaluate our method on three neural networks: LeNet-5, ResNet-20 and ResNet-50. Results show that current injection can reduce the accuracy degradation due to Stuck at Fault (SAF) and IR drop to 1%, and 5%, respectively.

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  • Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Qu ...
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 20 Pages 20200282
    Published: October 25, 2020
    Released: October 25, 2020
    [Advance publication] Released: October 06, 2020
    JOURNAL FREE ACCESS

    In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (VDD) with +1.6-V back-gate bias voltage (VBB). The best power density of 33.4-µW/MHz is reached at 0.5-V VDD with +0.8-V VBB. The least current leakage of 3-nA is retrieved at 0.5-V VDD with -2.0-V VBB.

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  • Gang Chen, Min Gong, Chun Deng
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 20 Pages 20200302
    Published: October 25, 2020
    Released: October 25, 2020
    [Advance publication] Released: October 08, 2020
    JOURNAL FREE ACCESS

    This paper presents a high speed dual channel 12.5 Gbps receiver for serial link communication. Each channel consists of a continuous time linear equalizer (CTLE), a novel 12.5 Gbps dual loop clock and data recovery (CDR) circuit based on phase interpolation with only simple CML and CMOS logic, which makes the design simplicity and more tolerant to process, voltage and temperature variations. A single PLL shared by the two channel CDRs generates quadrature clock phases and distributes high frequency clock to each CDR for data recovery. The 12.5 Gbps two channel receiver prototype was designed in 65-nm CMOS technology with phase interpolation based digital locked loop, occupying an active area of 1.3 mm2 and consuming a power of 300 mW from a 1.2 V power source.

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  • Lin Li, Jianhao Hu, Qiu Huang, Wanting Zhou
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 20 Pages 20200308
    Published: October 25, 2020
    Released: October 25, 2020
    [Advance publication] Released: October 15, 2020
    JOURNAL FREE ACCESS

    The accuracy of Convolutional Neural Networks (CNNs) has exceeded the human level in many fields, but the high computation complexity is one of the main challenges for CNNs applied in the mobile or embedded devices. In this paper, we provide a hardware accelerator scheme for the convolution operations in CNNs, which adopts the bit-serial systolic architecture. Implementation results show that the proposed scheme can reduce the area by about 64%, increase the maximum frequency by about 4.4 times and increase the hardware efficiency by about 1.2 times compared with the state-of-the-art Eyeriss architecture.

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