IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 14
Showing 1-15 articles out of 15 articles from the selected issue
LETTER
  • Jian Tan, Biyang Wen, Yingwei Tian, Ke Li, Jing Yang, Mao Tian
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140387
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    Stretch processing is an efficient method for pulse compression in chirp radar. A FPGA implementation of time-frequency transforming for stretch is presented. The key point is to calculate the spectrum points of interest using the segmental Time-Division Multiplexing (TDM) Discrete Fourier Transform (DFT), and the CORDIC algorithm is used to compute the complex multiplication. This approach shortens time and reduces memory size relative to FFT.
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  • Won Seob Jeong, Seung Hun Kim, Sang-Min Lee, Won Woo Ro
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140424
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    Single-ISA heterogeneous multi-core processors can provide energy efficient performance by properly assigning workloads on two types of cores in a processor: high performance large cores and low power small cores. However, traditional process scheduling mechanism is hard to support an proper workload distribution due to an overhead of fine-grained state monitoring and scheduling. To overcome this problem, we propose Swarm Processor System which supports hardware implemented workload scheduling mechanism. In the proposed system, each core chooses a proper workload by using special hardware modules in the core instead of the scheduler of operating systems. We compare Swarm Processor System against the traditional mechanisms, and found that the proposed method shows the closest energy efficiency to the oracle case with providing stable performance.
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  • Nam-Jin Oh
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140432
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    This paper proposes a novel low-phase noise Colpitts voltage-controlled oscillator (VCO) using a series LC network. For the series LC network, two capacitors are connected to each node of a parallel inductor-varactor tank (PLC). Each series connection node of the network is cross-coupled to the gates of switching transistors, and a large signal swing is achieved at each connection node. Also, the fixed biasing current sources of the differential Colpitts VCO are modified to operate as switched biasing current sources to lower the phase noise. Designed in 65 nm CMOS technology, the proposed VCO achieves a linearized tuning range from 3.73 to 3.97 GHz. The VCO consumes about 0.89 mW from a 0.4 V supply voltage, and achieves the phase noise of −123.3 dBc/Hz at 1 MHz offset. The calculated figure of merit of the VCO is about −195.5 dBc/Hz/mW.
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  • Changhwan Shin, Gwang-Geun Lee, Dae-Hee Han, Seung-Pil Han, Eisuke Tok ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140447
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    A ferroelectric field-effect transistor on a cellulose paper for nonvolatile memory application is fabricated by a low-cost solution-based-only fabrication process. A ferroelectric material, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), is used to obtain a wide threshold voltage (VTH) window of ∼20 V for the transistor on paper. An on/off current ratio of ∼102 is also obtained with a semiconducting channel material, Poly(3-hexylthiophene) (P3HT).
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  • Yuxiao Lu, Chaojie Fan, Lu Sun, Zhe Li, Jianjun Zhou
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140454
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: June 30, 2014
    JOURNALS FREE ACCESS
    A new window-opening low-power area-efficient switching logic for high speed successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. Unlike conventional SAR logic based on the shift register, the window-opening scheme minimizes the delay by putting the comparator results almost directly to DAC, and utilizes domino-based structure to reduce the capacitive load for comparator. According to pre-layout simulation in 65 nm CMOS technology, a 10 bit 100 MS/s SAR ADC with the new logic achieves a logic delay of 73 ps including DAC buffer delay, which is much lower than most SAR ADC.
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  • Zhen Xie, Yang Zhang, Jun Yang, Longxing Shi
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140466
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 11, 2014
    JOURNALS FREE ACCESS
    An improved memory system simulator based on DRAMSim2 is presented. The memory system simulator has been widely used in the design space exploration of the SoC (System on Chip). DRAMSim2 is one of the more common DDR2/3 memory system simulators. A memory system consists of the memory controller and the DRAM device. DRAMSim2 models the memory controller in a general way, which makes it impractical to faithfully track the behavior of a specific memory controller. In this work, we present an improved memory system simulator based on DRAMSim2. In response to the differences between the memory controller DRAMSim2 modeled and the practical controller, part of DRAMSim2 is modified and improved, considering the structure characterizations of the practical controller. Experiments show that the improved simulator properly matches the practical memory system.
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  • Mohammed S. BenSaleh, Syed Manzoor Qasim, Abdullah A. AlJuffri, Abdulf ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140474
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: June 30, 2014
    JOURNALS FREE ACCESS
    In this letter, a novel scalable and modular design of direct form sequential finite impulse response (FIR) filter using microprogrammed control unit is proposed that can be efficiently realized in field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The proposed design is suitable for sensor processing subsystem used in wireless sensor network (WSN) nodes. This is demonstrated by evaluating a sample 4-tap FIR filter on various FPGA platforms and ASIC technologies. The evaluation result shows good area/power efficiency and flexibility by using microprogrammed architecture for such applications.
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  • Daying Sun, Shen Xu, Weifeng Sun, Shengli Lu
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140493
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 14, 2014
    JOURNALS FREE ACCESS
    A novel digital control algorithm for a single-phase boost power factor correction (PFC) converter with fast dynamic response is presented. Based on the converter circuit structure, the track of the output voltage and the inductor current of next switching cycle is estimated in advance. The self-adjusting voltage control loop is adopted to improve the static and dynamic voltage regulation. Meanwhile, the current control loop is implemented only by the estimated output voltage and inductor current values, which simplifies the control loop and reduces the digital calculation burden. The single-phase boost PFC converter with the proposed digital control algorithm has been implemented via the field programmable gate array (FPGA). Experimental results indicate that the proposed control algorithm can improve the power factor, as well as the dynamic response of boost PFC converter simultaneously. The power factor is optimized more than 0.98, and the recovery time is less than 4 line cycles with small overshoot.
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  • Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140496
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    A basic design aspect of cache coherent Networks-on-Chip (NoCs) is the flow control mechanism. Since the minimum buffer size of virtual cut-through (VCT) switching is larger than that of the wormhole one, the VCT switching is traditionally regarded as an inefficient NoC flow control type. Yet, the scaling of semiconductor technology shrinks the transistor size, and reduces the criticality of buffer amount for NoC designs; the VCT switching may becomes a promising NoC flow control candidate. This paper performs a comprehensive comparison between the VCT and wormhole switching. Based on detailed RTL-level implementations, we evaluate the hardware costs with both deterministic and adaptive routing. Compared with the wormhole switching, the VCT one shortens the critical path by up to 27%, and induces less area and power overheads. Furthermore, the allocator in VCT routers exhibits a better scalability in area overheads. Thus, the VCT router is an efficient NoC flow control type.
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  • Yintang Yang, Xiaoxian Liu, Zhangming Zhu, Ruixue Ding
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140504
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: June 30, 2014
    JOURNALS FREE ACCESS
    The electrical performances of high-speed three dimensional integrated circuits (3-D ICs) are affected by temperature due to large integration densities, which may seriously affect the modeling and limit the reliability of circuits. In this letter, the parasitic resistance of through-silicon via (TSV) including temperature effect is studied. With the consideration of skin effect, Temperature Coefficient of Resistance (TCR) is introduced to evaluate the sensitivity of TSV resistance to temperature changes. It can be found that the sensitivity of TSV resistance to temperature changes significantly both with the frequency and radius of TSV. The expression of TCR can be simplified to the one obtained by neglecting the skin effect, which shows better applicability.
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  • Lili Wang, Xiangjun Xin, Linwei Zhu
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 14 Pages 20140517
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 04, 2014
    JOURNALS FREE ACCESS
    We propose and experimentally demonstrate a novel single-frequency erbium-doped fiber ring laser which features remarkable wavelength stability with the use of closed loop control. The system consists of a tunable FBG filter, erbium-doped fiber and a wavelength detector which detects the input wavelength to activate the closed loop control system to stabilize the output wavelength. The stability of the laser is investigated, the optimum operation wavelength range (1530–1570 nm) for the laser to achieve output power of 1.3 dBm, power variation of less than 0.2 dB and SMSR of up to 61.2 dB (0.02 nm resolution) is demonstrated.
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  • Zhang Jun-an, Li Guang-jun, Zhang Rui-tao, Li Jiao-xue, Wei Ya-feng, Y ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 14 Pages 20140533
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 11, 2014
    JOURNALS FREE ACCESS
    A 2.5 GHz Direct Digital Frequency Synthesizer (DDS) with spurious noise cancellation is presented. Seven auxiliary DDSs have been used as spur cancellers which can generate opposition signal to counteract the spurs in DDS’s output spectrum. Principle of spur cancellation and its implementation scheme is discussed. Key steps of spur cancellation procedure are also described. This DDS is implemented in a 0.18 µm CMOS technology, occupies 4.6 mm × 4.2 mm including bond pads. Measured performance is SFDR > 58 dB for output signal frequencies up to 1 GHz, more than 20 dB’s improvement is achieved comparing to its intrinsic SFDR performance.
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  • Jun Luo, Qijun Huang, Sheng Chang, Hao Wang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140562
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 11, 2014
    JOURNALS FREE ACCESS
    Compressed sensing has gained a wide application in image acquiring and reconstructing. Separable linear reconstruction has been shown to be effective in compressed imaging. This paper presents efficient hardware architecture based on adaptive sampling and separable reconstructing. By exploiting parallel properties in the architecture and timing scheme, high performance hardware has been proposed for both encoding and decoding sides. High performance Cholesky based matrix inversion has been implemented to solve the least square problem. Besides, high precision arithmetic element functions (reciprocal and square root reciprocal) have been presented by using of table interpolation and single iterated Newton-Raphson method. Experiment results show that the proposed hardware architecture can efficiently reduce the process time in encoding and decoding of a 512 × 512 image. The speedup is about 58× compared with the software-based approach (using LAPACK), and it is at least 1.92× faster than the state-of-the-art implementation.
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  • Kazuto Ohsawa, Atsushi Kato, Toru Kanazawa, Eiji Uehara, Yasuyuki Miya ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20140567
    Published: 2014
    Released: July 25, 2014
    [Advance publication] Released: July 11, 2014
    JOURNALS FREE ACCESS
    InGaAs is a promising material that can replace the current Si nMOSFET in CMOS because of its high electron mobility. To realize a high drain current density at a low supply voltage in InGaAs, the introduction of a heavily doped source is essential. We introduced an epitaxially grown n-InP source and obtained a high drain current density. However, short-channel effects were observed in a previous study; thus, we introduced extremely-thin-body III–V–OI InGaAs MOSFETs on a Si substrate. Accounting for the channel-thickness dependence, a drain current density of 2.04 A/mm at VD = 0.5 V and clear suppression of the short-channel effects were observed for a channel thickness of 10 nm.
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REVIEW PAPER
  • Shun-ichiro Ohmi
    Type: REVIEW PAPER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 14 Pages 20142006
    Published: 2014
    Released: July 25, 2014
    JOURNALS FREE ACCESS
    The importance of Si surface flatness on metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) high-k gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was described. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. Si surface root-mean-square (RMS) roughness was well controlled by changing the annealing temperature from 700 to 1000°C. Si surface RMS roughness after 1000°C/1 hr annealing was 0.078 nm for Si(100) and 0.082 nm for Si(110), respectively. Clear dependence of electrical characteristics of MOS diodes such as equivalent oxide thickness (EOT) and leakage current on the surface RMS roughness of Si(100) and Si(110) was observed, and the electrical characteristics were remarkably improved by decreasing of surface RMS roughness. The MOSFET characteristics with HfON gate insulator fabricated on Si(100) substrates after flattening process were also improved.
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