The traditional cavity ring-down signal processing system usually consists of a computer and a high-speed data acquisition card, and it has some problems such as large volume, high cost and inconvenience to carry in practical engineering applications. Aiming at the deficiency of traditional signal processing system, a compact real-time data acquisition and processing scheme is proposed and realized based on the Xilinx ZYNQ chip. In which, the FPGA and ARM core integrated into the ZYNQ chip are used to replace the data acquisition card and PC, and the whole system are built and implemented on the circuit board. The experimental results show that, compared with the traditional signal acquisition and processing system, the relative deviation of V-shaped cavity decay time between the two systems is 0.38%, and the repeated measurement standard deviation of the new system is much smaller, which is about 1/3 of the traditional system. Furthermore, the ENOB (Effective Number of Bits) and SFDR (Spurious-Free Dynamic Range) of the new system are measured as > 10.4 bit and > 72dB respectively.
A novel three-level (TL) converter topology is proposed in this paper. The primary side of the proposed converter consists of two asymmetric half-bridge inverters, which are connected in series. The rectifier stage is composed of two parallel full-bridge-rectifier (FBR) which use the same diodes as the common current path. The asymmetrical-PWM control is employed to regulate output voltage. Compared with the traditional TL converters, the circulating current can be significantly reduced. Moreover, all the switches can achieve ZVS performance with a small leakage inductor over wide load range. The parallel connection of the two FBR also helps to reduce the current ripple of the filter inductor, leading to high density switching converter design. In this paper, a laboratory prototype (480-600Vdc input, 96Vdc/12A output) based on the proposed converter is built to validate the theoretical analysis.
This paper presents a compact 24-32GHz high-linearity broadband, fully integrated amplifier which is designed in 130-nm SiGe (BiCMOS). The principle of improving the linearity of degeneration inductor and the effect of the driving stage on linearity are analyzed. To achieve flat broadband, the transformer is also used in the inter-stage matching. Output matching for low insertion loss networks has been selected carefully. The amplifier demonstrates a small signal gain of 11.3dB range from 24GHz to 32GHz with a gain flatness of ±0.5dB. Measurements show a maximum power added efficiency (PAE) of 18.54% with output 1dB compression power for 7.6dBm at 32GHz.
Hybrid DC circuit breaker is one of the most equipment in high voltage direct current (HVDC) systems. It includes numbers of power electronic (PE) devices and high efficiency isolated power supply is required to control these PE devices. The phase-shifted full-bridge (PSFB) converter is a popular topology for isolated power supply. However, the traditional PSFB converter has some well-known drawbacks. To solve these drawbacks, a novel ZVS FB converter is proposed in this paper. In the primary side of proposed converter, four FB switches, two main transformers and one shared capacitor constitute two half-bridge inverters. At the rectified stage, two FB rectifiers are connected in series by sharing diodes. This structure allows the proposed converter to achieve wide zero-voltage switching range and reduced filter requirement, which make the proposed converter well suited for the power supply for hybrid DC circuit breaker. The performances of proposed converter are verified with an experimental prototype.
In this paper, we compare the distortion and power characteristics between AlGaN/GaN high-electron-mobility transistors (HEMTs) with different epi-structures. Third-order intermodulation distortion (IM3) measurement evaluates distortion characteristics, and on-wafer load and source-pull measurements evaluate the power performance. The results show that the AlGaN/GaN HEMTs directly fabricated on GaN substrates without nucleation layer perform better than those fabricated on SiC substrates. Furthermore, the distortion performance is compared with and without field plate.
In order to reduce the main memory energy of the IoT terminal, STT-MRAM is used to replace DRAM to save refresh energy. However, the write performance of STT-MRAM cells is worse than that of DRAM. Our previous work proposed a hybrid DRAM/STT-MRAM main memory and fast data migration to reduce the adverse effects of poor write performance of STT-MRAM cells with negligible performance overhead. This article optimizes the migration algorithm and experiment scheme: 1. Reduce the storage overhead of the algorithm. 2. Realize the continuous work of the algorithm. 3. Consider the impact of system standby time on main memory energy. The results show that compared with our previous work, the storage overhead of the algorithm is reduced 99.8%. When the system standby time is zero, the energy of the hybrid main memory (including the energy of the algorithm) is reduced by 4% on average compared to DRAM. The longer the system standby time, the more energy saving.