IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 9, Issue 8
Displaying 1-11 of 11 articles from this issue
  • Long Chao, Wu Xiongbin, Liu Bin, Li Lun, Xu Xing'an
    2012 Volume 9 Issue 8 Pages 731-738
    Published: April 16, 2012
    Released on J-STAGE: April 16, 2012
    In this paper, we propose a passive array calibration method based on the adaptive hybrid algorithm (AHA) for the engineering applications of high-frequency surface wave radar (HFSWR). This method converts array error estimation into joint estimation of multi-parameters and gets the optimal solution estimation by using improved hybrid algorithm. Simulation results and field experiment data show that this method significantly improves the performance of spatial spectrum algorithm in the array calibration for mutual coupling errors of distributed HFSWR.
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  • Takashi Mitsui, Kazutaka Hara, Masamichi Fujiwara, Jun-ichi Kani, Masa ...
    2012 Volume 9 Issue 8 Pages 739-744
    Published: April 16, 2012
    Released on J-STAGE: April 16, 2012
    A simple and scalable wavelength division multiplexing/time division multiple access passive optical network (WDM/TDMA-PON) system is demonstrated that uses spectral slicing and forward error correction (FEC) with a Reed-Solomon (255, 239) encoder in burst mode upstream transmissions. Receiver sensitivities are improved to -33.5, -34.9 and -35.5dBm at a sliced bandwidth of 100, 200 and 400GHz with FEC. Moreover, the dispersion penalties after a 20km transmission are only about 0.6 and 0.4dB at a bit error rate (BER) of 10-10 at 200 and 400GHz, respectively.
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  • Ho-Young Park, Sang-Hyeok Yang, Suki Kim, Kye-Shin Lee, Yong-Min Lee
    2012 Volume 9 Issue 8 Pages 745-751
    Published: April 16, 2012
    Released on J-STAGE: April 16, 2012
    This paper proposes a 10-bit parasitic insensitive capacitive DAC with time-mode reference voltage generator for high resolution LCD drivers. In this architecture, the parasitic insensitive operation is achieved by modifying the switch control scheme of the DAC. Furthermore, the time-mode reference voltage generator replaces the conventional resistor divider scheme, which reduces the size of the reference generation circuitry and enables programmable DAC reference voltage. The proposed DAC was designed with CMOS 0.35µm technology. The maximum INL and DNL showed -0.049LSB and -0.026LSB even with 10% parasitic capacitance.
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  • Maryam Amirhoseiny, Zainuriah Hassan, Ng ShaShiong
    2012 Volume 9 Issue 8 Pages 752-757
    Published: April 17, 2012
    Released on J-STAGE: April 17, 2012
    Photo-electrochemical etched Si layers were prepared on n-type (110) oriented silicon wafer. SEM results shows groove structure for etched Si (110). The photoluminescence (PL), Fourier transformed infrared (FTIR) absorption and Raman spectroscopy of etched Si (110) as a function of etching time was studied. All samples showed a PL peak in the visible spectral and the intensity of the PL peak increases with rising of the etching time. It is also found that the Raman peak of the etched Si samples is red shifted and its intensity significantly decreases as the etching time increases.
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  • Soonyong Lee, Yeonsik Yu, Kyeol Kwon, Koichi Ito, Jaehoon Choi
    2012 Volume 9 Issue 8 Pages 758-764
    Published: April 20, 2012
    Released on J-STAGE: April 20, 2012
    A flexible diversity antenna using zeroth-order resonance (ZOR) for WBAN applications is proposed to improve performance and overcome multipath fading. The dimension of the proposed diversity antenna, including the system ground, two antenna elements, and the decoupling network is 44mm × 35mm × 0.127mm. When the antenna is located on a semi-solid flat phantom with equivalent electrical properties of a human body, the S11 and S22 values of the proposed antenna at 2.45GHz are -22.8dB and -25.4dB, respectively. The measured specific absorption ratio (SAR) values of the antenna elements #1 and #2 are 0.54W/kg and 0.75W/kg (1g tissue) and mean powers delivered from the two ports are almost identical since the proposed antenna has a measured ECC of 0.021MEG ratio of 0.33dB at 2.45GHz.
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  • Jianfeng Zhang, Hengzhu Liu, Wenmin Hu, Dongpei Liu, Botao Zhang
    2012 Volume 9 Issue 8 Pages 765-771
    Published: April 23, 2012
    Released on J-STAGE: April 23, 2012
    Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm is an effective implementation of trigonometric function, and it has been widely applied in digital signal processing. In this paper, we propose a novel CORDIC architecture based on Scaling Free (SF) theory, which adopts adaptive recoding method to reduce the iterations and eliminate the scaling factor. The proposed scheme has been synthesized using 65nm CMOS technology with standard cell library. Compared with SFB4C, our scheme saves 21.11% to 34.64% hardware-overhead with no performance penalty.
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  • C.H. Lim, W.Q. Tan, T.S. Lim, V.C. Koo
    2012 Volume 9 Issue 8 Pages 772-778
    Published: April 24, 2012
    Released on J-STAGE: April 24, 2012
    Inertial navigation unit (INU), which is commonly composed of three orthogonally aligned accelerometers and gyros, is well known for its short term measurement accuracy in position, velocity and attitude. However, such measurement accuracy degrades with time due to various types of errors. In this paper, a practical approach is proposed to estimate both the deterministic and random errors of an INU. The deterministic errors, which include bias and scaling errors, can be estimated through a simple experimental setup; while the random noise is modeled using Allan Variance (AV) analysis method. The empirical values of the errors are then fed into the INU's system model for error correction using Kalman filtering. Finally, the calibrated INU shows promising results in preserving long term accuracy of the motion sensor.
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  • Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru
    Article type: REVIEW PAPER
    2012 Volume 9 Issue 8 Pages 779-794
    Published: April 25, 2012
    Released on J-STAGE: April 25, 2012
    SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers. This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for the highly reliable, high speed and low power NAND flash memory based SSDs.
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  • Hiro Akinaga, Hisashi Shima
    Article type: REVIEW PAPER
    2012 Volume 9 Issue 8 Pages 795-807
    Published: April 25, 2012
    Released on J-STAGE: April 25, 2012
    We review recent progresses in Resistive Random Access Memory (ReRAM) technologies together with difficult challenges and prospects. ReRAM is one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, a brief historical overview of the research is provided. The technological overview is reported with the epoch-making achievements. Second, the current understanding in terms of the operation mechanism is shown followed by the technical assessment, especially the advantages of ReRAM. Finally, we summarize the challenges facing the ReRAM technology and the prospects.
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  • K. D. Sadeghipour
    Article type: LETTER
    2012 Volume 9 Issue 8 Pages 808-814
    Published: April 25, 2012
    Released on J-STAGE: April 25, 2012
    In this paper, a new accurate track and latch comparator circuit is presented. The Offset voltage of latch is compensated by negative feedback loop and the low offset voltage is achieved without pre-amplifiers. The pull up devices in modified regeneration latch is turned off to reduce quiescent current of comparator within the tracking phase. The Monte-Carlo simulation results for the designed comparator in 0.18µm CMOS process show that equivalent input referred offset voltage is 200µV at 1 sigma while it was 26mV at 1 sigma before offset cancellation. The comparator dissipates 400µW from a 1.8V supply while operates in 500MHz clock frequency. The power consumption improvement is up to 33% over previously reported structure.
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  • S. Hassan Mirhosseini, Ahmad Ayatollahi
    Article type: LETTER
    2012 Volume 9 Issue 8 Pages 815-821
    Published: April 27, 2012
    Released on J-STAGE: April 27, 2012
    In this paper a low consumption 10bits pipelined analogue to digital converter (ADC) by using a new operational transconductance amplifier (OTA) is introduced. The ADC is designed to work at 100MHz with 1 volt bias voltage in a CMOS 90nm technology. The simulation results at frequency of 5MHz show the spurious free dynamic range and signal to noise ratio of 66dB and 58.4dB (9.4 ENOB) respectively. The power consumption for the designed ADC including digital and analogue parts is 14.4mW.
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