This paper presents a high-gain differential CMOS low noise amplifier (LNA) for 3.1-10.6GHz ultra-wideband receivers. A novel structure that combines capacitive cross-coupling common-gate topology with common-source topology is proposed, which increases the power gain greatly and imposes little impact on other performances of the LNA.The LNA is designed in the TSMC 0.18µm CMOS technology. Post-layout simulation results show that the LNA achieves a power gain of 14.9 ∼ 16dB and a noise figure of 3.5 ∼ 4.9dB with a current consumption of 6.3mA from a 1.8V power supply. The layout area is 0.7 × 0.9mm².

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A higher order ΔΣ Modulator (DSM) is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The existing second order, single stage, single bit, unity or non unity feedback gain (κ), discrete DSM cannot be used for the full range (-κ to +κ) of an input signal since the DSM becomes unstable when the input signal is above ±0.7κ. In the present paper, a second order, single stage, discrete DSM with input signal dependant feedback gain and an input signal dependant DSM operating period is proposed. The proposed DSM can operate with a wide range of input signals without causing instability.

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This letter investigates a decision-fusion based image quality metric that performs multi-feature oriented method in contrast to individual feature as done by general methods. The comprehensive image quality feature is generated based upon the statistical method of Canonical Correlation Analysis (CCA), by which diverse quality features are incorporated. The efficient design of the proposed algorithm allows more accurate and stable quality prediction for complicated distortion, and another advantage over others is the flexibility of parameters tuning due to the employment of prior knowledge of the testing database.

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In this paper we present an automatic method for instruction-set extension generation. This method is based on a concept we called it center of gravities which uses inherent parallelism of input graph to achieve higher performance Instruction-Set Extension (ISE). The algorithm is fast and does not impose any limitations on the number of Input/Outputs. Results show speedup increase at DFG level up to 9x for some DFGs.

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In this paper, a wideband dual rectangular loop antenna over an EBG surface is proposed for low profile wireless applications. A low frequency mushroom-like EBG surface is used as the antenna ground plane. In comparison with a PEC ground plane, design of antenna above an EBG ground plane results in 60% reduction of the structure thickness. The investigated antenna is designed for circular polarization. It is shown that the axial ratio bandwidth (<3dB) and return loss bandwidth (<10dB) of the dual rectangular loop antenna above the designed EBG surface are 18% and 14%, respectively. The simulated and measured results are in good agreement.

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This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

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This paper describes a 4bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full flash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADC's performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46MHz input signal and 3.94 ENOB for 1046MHz input signal at 2GHz sampling rate. At 2GSample/s, the current consumption is 45mA including digital logic with 1.8v power supply voltage. The proposed 4bit ADC is designed with 0.18um CMOS technology.

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For the successful transmission of complex signals through frequency multipliers, high order analysis of IMD responses for a frequency tripler is performed and the optimum solutions for the harmonic injection technique is presented to suppress the high order IMDs in the 3^rd zone. From the 7^th order analysis, optimum injection was found to suppress IMDs in the 3^rd harmonic zone and their optimum phases are shown to be apart by 180 degrees due to the even-ordered Volterra products of the injection. The measurement results showed IMD suppression better than 30dB, which is consistent with the analysis and the simulated results.

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A visual prosthesis is an artificial sensory organ that transmits visual information to a blind person by electrically stimulating residual neurons in the visual nervous system. Such a system requires a large number of stimulating electrodes: It is technically difficult to connect a stimulator placed behind the ear to each of the stimulating electrodes over any significant distance with high reliability. We propose a visual prosthesis containing a multiplexer that is separately placed from the stimulator unit. The array of stimulating electrodes is connected to the stimulation unit through a multiplexer. The stimulating electrodes and multiplexer are placed onto the suprachoroidal space. The stimulation unit consists of a metal case and a coil and is implanted in the postauricular region of the cranium. The multiplexer and the stimulator unit are connected by a cable composed of six wires. Incorporating the multiplexer enables us to control of a large number of electrodes using a small number of conductors in the cable. We have developed a system with 100 electrodes which is powered and controlled wirelessly. Then we have confirmed that the proposed system functions successfully both in vitro and in vivo.

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