This paper presents a design of an elliptic curve coprocessor over GF(p) with side-channel analysis countermeasures and fast implementation schemes, which can be used for all elliptic curve cryptographic algorithms, such as ECC and SM2. The proposed coprocessor can resist side channel analysis and is implemented basing on the C*Core-C0 platform. Using SMIC 0.13-µm CMOS technology, synthesis results show that our coprocessor can perform one 256-bit elliptic curve scalar multiplication over the prime field in 8.35 ms at 50 MHz with only 1.98 mW and 17.7K gates. The proposed coprocessor outperforms other coprocessors in terms of the overall performance of area, power, speed and security, which is quite suitable for smart IC card.

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In this paper, a new method is proposed to reduce the power consumption and occupied area of successive-approximation register analog to digital converters (SAR ADCs). The proposed solution is based on pre-charged capacitor array consisting of identical unit capacitors. According to the new method, switching operations to determine the least significant bits are replaced by adding pre-charged capacitors to the main capacitor array. This method is applicable for binary-weighted capacitor arrays with different switching schemes. With the presented method, switching energy and the number of unit capacitors are reduced by at least 50%.

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This paper presents a compact driver module for InP Mach-Zehnder modulator (MZM). The size of the driver module is 14 mm × 8 mm × 2.8 mm. We reduce the size of this driver module by integrating two channels for the driver IC, which doesn’t require any external bias tee, and by making the driver package small. With this driver module and InP MZM module mounted on evaluation board, we obtained a well separated 16-QAM constellation at the speed of 28 Gbaud.

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We report on AlGaN channel metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) for the first time. The insulator of 10-nm SiN_x was deposited by plasma enhanced chemical vapor deposition, which induced a low reverse and forward Schottky leakage. A very high breakdown electric field of 1.8 MV/cm was reached with a gate-drain distance of 2 µm. The breakdown voltage increased non-linearly with the gate-drain distance and reached 1661 V with a gate-drain distance of 20 µm. As temperature increases from 25 to 275°C, the saturation drain current decreases slightly by 20% from 211 to 169 mA/mm and the on-resistance increases only by 24%.

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Energy harvesting is a technique that captures an effective power source. However, the energy obtained from power resources in the environment is insufficient, as only low levels of voltage/current can be generated from it. Therefore, the power consumption of logic circuits for energy harvesting has to be reduced. To achieve low power consumption, we may consider two low-power techniques: the adiabatic logic circuit and the sub-threshold CMOS logic circuit. In this paper, we propose a new CMOS logic circuit that combines the adiabatic logic circuit with the sub-threshold logic circuit. The proposed circuit employs two-phase clock supply voltages that have different amplitude and frequency. We design and implement NAND, XOR, half-adder, full-adder, and 4 × 4-bit multiplier circuits using the proposed method. The simulation and the measurement results show that the proposed circuit has an ultra-low-power characteristic compared with the conventional circuit.

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The research of an ultra-broadband power amplifier based on TGF2023-2-02 GaN HEMT which operates in the frequency ranging from 3 GHz to 8 GHz, is presented in this paper. The transistor of GaN HEMT is modeled and a frequency compensation and multi-side impedance matching approach are adopted for broadband impedance matching of amplifier. And a fan shaped micro strip line is implemented in the input matching network to achieve the wideband higher gain features. The measured results show that the amplifier module provided more than 37 dBm output power with minimum small signal gain of 9.8 dB over 3–8 GHz. The saturated output power is 38.3 dBm under DC bias of Vds = 28 V, Vgs = −2.75 V at the frequency of 5 GHz.

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Mode-division multiplexing (MDM) is widely researched, and we are researching mode converter by using multi-mode interference (MMI) waveguide. Wavelength division multiplexing (WDM) must be used in addition to the MDM, however, wavelength dependency exits for MMI in general as it works based on the interference of light. In this paper, we analyze the wavelength dependency of the MMI 0^th to 1^st mode-converter theoretically. As a result, we clarify the design scheme to suppress the wavelength dependency. Moreover, we show the sufficient performance of less than 1.0 dB in entire C-band for highly confined waveguide (Si/SiO₂ waveguide) as a design example.

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An accurate and low-cost technique is proposed for sinusoidal jitter and random jitter estimation in high-speed ADC test. Exploiting the fact that clock jitter is modulated by the slope of input signal, the proposed method can simultaneously extract both information for sinusoidal jitter and random jitter with a single high frequency test. The proposed method is computationally efficient since only one FFT, one IFFT and few simple arithmetic operations are involved. Compared with existing dual-frequency tests and single-frequency tests, both hardware overhead and data acquisition time are saved significantly. Theoretical analysis and simulation results validate the computational efficiency and test accuracy.

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Testing of interconnect resources is one of the most important parts in FPGA testing, since most of the transistors in the chip are dedicated to interconnections. Conventional testing methods are no longer as efficient as before because of the various new types of interconnections and a lack of enough input output blocks (IOBs) in the FPGAs that are based on general routing matrix (GRM). This paper presents a new automatic method for testing FPGA interconnect resources in GRM-based FPGAs. This new method, testing line segments and programmable interconnect points (PIPs) in different stages, is applicable to all kinds of GRM-based FPGAs. Experimental results show that a total of 152 test configurations are sufficient to achieve 99.2% and 99.7% fault coverage for line segments and PIPs in Xilinx XC4VLX15 FPGA respectively and to largely reduce the number of IOBs required in the testing.

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A 64 Mbit phase change memory chip is fabricated in 40 nm CMOS technology. An improved fully-differential sense amplifier with a bias voltage instead of the reference resistor branch is proposed to diminish the chip area. The transient response capability of the proposed sense amplifier is improved by removing the large parasitic capacitance of bit line in the feedback network. Smaller parasitic capacitance is also obtained by the separated programming and reading transmission gates to speed up the read operation. The hierarchical bit line architecture is used to reduce the length of bit line, and thus favorable read performance can be achieved.

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