A digital integrated circuit to realize multi-chip phase synchronization of fractional-N PLL with local oscillator divider is designed. An offset of fractional frequency ratio is added in phase difference calculation, which effectively avoids the large calculation error under some special fractional frequency ratios. Different from traditional one-time synchronization, a synchronization method with tracking mode is proposed, which can further reduce the phase error. The test result of the chip finished in 65nm COMS shows that the method of tracking mode and adding the fractional frequency ratio’s offset are effective to reduce the error of phase synchronization to about 0.2°.
Inaccurate capacitance significantly increases the DC-Link ripple voltage of active power decoupling circuit (APDC). To solve this problem, a high-precision online capacitance estimation method is proposed. This method converts the AC components of decoupling capacitor into the sum of DC component and AC component with 8 times grid frequency, which is beneficial to the extraction of DC component. This DC component replaces the AC component to effectively eliminate the periodic capacitance mutation, and accurately estimate the capacitance. Based on the capacitance, the DC-Link ripple is controlled with the set scope. Experimental results verify the effectiveness of the proposed method.
In this letter, we proposed a highly linear mixer-first receiver with a discrete-step attenuator (DSA) and a noise-shaping TIA. A resistor-reuse technique is devoted to improving linearity and attenuation flatness of the DSA with frequency independance, and a negative impedance chopping method is proposed to reduce the in-band noise of the TIA. Measurement results show that the receiver achieves >13dBm IIP3 and in-band noise floor has been depressed by 4dB, with only consuming 2.82mW under 1.3V supply.
This paper presents a low temperature coefficient and wide temperature range bandgap reference with high power supply rejection. High temperature curvature compensation of this circuit is accomplished by MOSFET transistors operating in the subthreshold region. With the proposed piecewise compensation technique, the temperature range is extended. At the same time, a pre-regulator structure is adopted to improve the line sensitivity and suppress the ripple of the power supply. The novel bandgap reference is proposed and verified in 180nm CMOS process. The measured VREF is 1.18V at 3.3V power supply voltage, and the static current of the circuit is 75uA. Over the wide temperature range of -60∼160°C, the temperature coefficient achieves 5.72ppm/°C, and the power supply rejection is -93.26dB at low frequency.
In this paper, a method for 0.1µm InP HEMT parameters extraction using Full-wave Electromagnetic (FW-EM) simulation is proposed. The parasitic capacitances are divided into pad and electrode capacitances to describe the distributed effects. Based on the extrinsic equivalent circuit, five standards are proposed to determine the parasitic capacitances and inductances using FW-EM simulation. Additionally, as ohmic contact resistance cannot be acquired using FW-EM simulation, parasitic resistances are determined using a Cold-Fet method without forward gate bias. Multi-bias extraction for various device sizes has been used to validate the accuracy and robustness of the suggested extraction approach, and the results indicate good agreement from 0.1 to 40GHz.
The use of power electronics has increased in everyday applications such as portable devices, biomedical, electric vehicles, etc. One of the major issues in such devices is an overshoot observed in the output voltage. The desired output in the converters comes with the over/undershoot problem which affects their performance. State-of-the-art evaluation measures such as overshoot percentage, settling time, and rise time only analyze a certain aspect and do not estimate the true performance of the system. In this work, we propose two new evaluation measures to analyze the performance of the converters overcoming the limitations of existing measures, i) Total over-under shoot (TS) and ii) First shoot second shoot (FSSS). We also propose one composite evaluation metric Aoun stability-1 to provide a single quantitative measure to analyze the performance of the system. A basic converter with a PID controller and Machine Learning based model is used to highlight the limitations of the existing metrics and strengths of the proposed metrics. Experimental results also highlight the advantages of the proposed measures. The proposed work is also expected to attract attention from the signal processing community facing similar issues in many applications.