This letter presents a broadband compact watt-level high-efficiency power amplifier (PA) in 0.35-µm SiGe BiCMOS process. A four-way triple-tank-based power combiner is introduced and theoretically analyzed in detail with the consideration of the undesired inductor in the third tank. The coupling coefficient and the uncoupling resonant frequencies of the tanks can be adjusted to compensate for the deterioration caused by the undesired inductor, achieving broadband and low-loss matching. The proposed PA operates over 4.4-6.4GHz and exhibits a peak gain of 35.2dB, a maximum saturated output power (Psat) of 30.5dBm, and a peak power added efficiency (PAE) of 34.8% at 5.4GHz.
In this paper, a 4.5-5.5GHz wideband high efficiency Doherty power amplifier (DPA) MMIC using a novel compensation technique is proposed. The phase difference and output capacitances of the carrier and peaking PA are analyzed and compensated accurately in a wideband. Thus a sufficient load modulation of the DPA is obtained in a broadband. To verify the proposed design methodology, a broadband high-efficiency DPA MMIC is designed and fabricated in a 0.25µm GaN-HEMT process for 5G massive MIMO applications. The measurement results illustrate that power added efficiency (PAE) is 44.8%-52.2% at the saturated output power (Psat) of 39.8-40.8dBm, the PAE at 6-dB output back-off (OBO) is 40.9%-43.9%, and the small-signal gain is 12.5-13.9dB. The proposed DPA demonstrates state-of-the-art saturated and 6-dB back-off PAE among published C-band broadband GaN MMIC DPAs.
In this study, a novel active disturbance rejection controller (ADRC) is proposed to significantly improve the speed control performance of permanent magnet synchronous motor (PMSM). The conventional ADRC, namely linear active disturbance rejection controller (LADRC) and nonlinear active disturbance rejection controller (NLADRC), both them have their own merits and drawbacks. Thus, an enhanced switching active disturbance rejection controller (ESADRC) is developed to counteract the impacts of the speed-loop for the PMSM. The proposed ESADRC comprises several novel components including a novel tracking differentiator (TD), a novel switching extended state observer (SESO), a novel switching state error feedback (SSEF), and a cascaded extended state observer (ESO). The cascaded ESO is responsible for estimating the remaining disturbance after the SESO. Through comparative verification, it is verified that the proposed ESADRC outperforms the traditional ADRCs in terms of performance.
This paper presents a high-precision, low-power CMOS temperature-to-digital converter (TDC) for detecting MEMS reference frequency sources on-chip temperature. This TDC uses a bipolar transistor as the core device for temperature measurement and a second-order Sigma-Delta ADC to read the temperature information. In order to improve the accuracy, the PTAT bias circuit with finite current gain compensation resistor and Dynamic Element Matching (DEM) circuit with Bank-Swap structure is employed in the temperature front-end circuit, respectively. In the ADC design, Analog T-switches (AT-Switch) with complementary structures are employed to reduce the leakage current of MOS switches in a fully differential switched-capacitor integrator to improve the accuracy further. Implemented in TSMC 180nm CMOS, the TDC occupies 0.135mm2. The measurement results show that the average power consumption of the circuit is 95µW (@27°C) at a supply voltage of 1.8V. After temperature curve fitting, an inaccuracy of ±0.85°C (3σ) is achieved from -40°C to 85°C, which meets the requirements of the FBAR (Flim Bulk Acoustic-wave Resonator) oscillator for temperature compensation.
A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate the input-referred offset voltage (VOS), which dictates the minimum required bitline swing for a reliable read operation of static random access memory (SRAM). The data-aware coupled capacitors are employed to dynamically tune the driving ability of sensing transistors according to the data supposed to be read, thus improving the offset tolerance of sense amplifier (SA). Compared with the conventional current latch-type SA (CLSA), the simulation results in 55-nm CMOS technology show that the proposed scheme achieves more than 4.17X of the standard deviation of VOS (σOS) reduction across the range of supply voltage from 0.6V to 1.2V and reduce the read energy consumption and read delay to 54.9% and 45.5% respectively. Furthermore, the proposed scheme reduces the σOS by 2.19X compared to DIBBSA on average.