In this paper, the Indium Gallium Zinc Oxide (IGZO)-Oxide-P-filler (IOP) structure is proposed to improve the poor erase performance of three-dimensional (3D) NAND flash structures using IGZO channel. First, the erase performance of the polysilicon channel and the IGZO channel of the 3D NAND flash structure were compared. During this simulation, the IGZO channel displayed a low 0.06 V erase performance. To solve this problem, the proposed IOP structure was able to produce a memory window of 5.29 V. Based on these results, we confirmed that the IOP structure can greatly improve erase performance, which is the largest obstacle in using the IGZO channel.

This paper presents a DLL based clock multiplier with a novel spur reduction technique. By randomly selecting delay line with pseudo random number generator (PRNG), the proposed scheme reduces the output spur due to delay cell mismatches. Rotational digitally controlled delay line (DCDL) is also proposed for seamless generation of clock edges even at random delay line switching. The clock multiplier is designed in 0.18 µm CMOS process and achieves 5∼11 dB reduction of spur while consuming 169.4 µW for 16 MHz. The core area is 0.608 mm².

This paper proposes Full-Parallel Convolutional Neural Networks (FP-CNN) for specific target recognition, which utilize the analog memristive array circuits to carry out the vector-matrix multiplication, and generate multiple output feature maps in one single processing cycle. Compared with ReLU and Tanh function, we adopt the absolute activation function innovatively to reduce the network scale dramatically, which can achieve 99% recognition accuracy rate with only three layers. Furthermore, we propose a performance metrics function to resize the scale of the FP-CNN for solving different classification tasks. With the help of such design guidelines, the FP-CNN can still achieve over 96% recognition accuracy under the condition of 95% yield of memristor crossbar array and 0.5% Single-Pole-Double-Throw switches (SPDT) noise.

A 1-1-1 MASH delta-sigma TDC with a simpler structure was designed using an error feedback structure. The proposed 1-1-1 MASH delta-sigma TDC modulator has a single subtractor without any explicit integrator. Each modulator stage is composed of a subtractor, digital-to-time converter, and a quantizer. The subtractor generates the timing difference between input signal interval and the feedback signal interval. The digital-to-time converter (DTC) adds or subtracts fixed delays depending on the subtractor output and the quantizer values. The proposed circuit was designed using a 180 nm CMOS process. The simulation results show a resolution of 2.07 ps and a valid bit count of 11.5 bits at a sampling frequency of 50 MHz. The area is 0.14 mm², and the power consumption is 1.34 mW.

Harmonic currents in a grid-tie inverter system not only increase the inverter loss but also reduce the inverter efficiency. Harmonic detection is the precondition of harmonic control. Among the various methods, sliding discrete Fourier transform (SDFT) based algorithms has found wide and popular applications due to advantages like simplicity and excellent selectively filtering properties. However, SDFT suffers from disadvantages like slow dynamics and large memory occupation. In order to alleviate these drawbacks, an improved SDFT is proposed to detect the system harmonics. The proposed SDFT not only maintains the advantages of simplicity and selectively filtering properties but also features fast transients, around 1/6 fundamental cycle for typical harmonics in three-phase application, which is much shorter than the one-cycle settling time of the conventional SDFT. Simulation and experimental results show the validate effectiveness of the proposed method.

For switched-capacitor (SC) integrator, an exponent-scalable method to obtain very small capacitance spread and large time constant is presented. Based on Nagaraj-89 SC integrator, an additional SC feedback branch with an extra clock phase is employed, resulting in capacitance spread to the 3rd power in z-domain transfer function. Furthermore, with (N − 2) additional SC feedback branches using (N − 2) extra clock phases, capacitance spread to the Nth power can be achieved in z-domain transfer function. Compared with previous SC integrators, this proposed exponent-scalable method is analyzed, and it is verified by simulation that larger time constant can be realized with less capacitor area. Moreover, Monte-Carlo simulation shows low relative standard deviation of time constant is also maintained.

A novel low complexity TDC/ADC hybrid reconstruction read-out circuit (ROIC) is proposed for LiDAR. Compared with other TDC-based receivers, the proposed circuit can provide a higher sampling speed, while consuming less power than ADC-based receivers. The circuit structure is constructed based on a sampler circuit to realize full waveform reconstruction. To further reduce power consumption, a Time Control Technique (TCT) is utilized to enable the sampler circuit to work only when needed. More specifically, the bandwidth, gain and input referred noise current spectral density of analog front-end (AFE) circuit are set as 150 M, 83 dB and 3.25 pA/sqrt (Hz), respectively. The experiment results demonstrate the feasibility that the sampler circuit can reach more than 3 GHz sampling frequency with only 2.8 mW power consumption.

In this paper, a time-interleaved 10-GS/s 8-bit analog-to-digital converter (ADC) fabricated in 0.18 µm SiGe BiCMOS technology has been demonstrated. A 4 × 4 input multiplexer with good isolation and wide input bandwidth is proposed, which enables the ADC to support 1/2/4-channel sampling modes. In the track-and-hold (THA) stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the overshoot effect of the SEF output. The ADC achieves spurious free dynamic range (SFDR) > 52 dBc and effective number of bits (ENOB) > 6.8 in low input frequencies. The analog input bandwidth is 5.6 GHz.

This paper is the first report on transmission loss of screen-printed metallization of transmission lines at frequencies ranging up to 340 GHz. We observed that the printed transmission lines exhibited significantly reduced transmission losses when compared to conventional lines on the commercialized impedance standard substrate (ISS). The conductivity of Ag metallization was considered the reason for this reduced loss. Though degradation of the loss was observed in transmission lines approximately 3 years post fabrication, the printed line retains a smaller loss than conventional lines on the ISS. Further, despite the printed line having inferior production reproducibility, the screen-printed technology was considered to be an improved solution for the fabrication of millimeter-wave circuits, even in the 300 GHz band.

A kind of broadband power amplifier for wide-band coverage of the next-generation base station communications systems is obtained through using GaN HEMT transistor CGH40010 supplied by CREE as carrier or peak power amplifiers, and a novel load modulation network (LMN) is presented in this paper. With continuous wave (CW) measurements, the results for the obtained Doherty power amplifier (DPA) show that the saturation drain efficiency is between 61% and 71%, the 6 dB back off efficiency is greater than 35%, and the maximum efficiency is 52% in the 2.8–4.0 GHz frequency range. The performance of this improved DPA is more excellent than that of the unimproved one. Furthermore, 20 MHz long term evolution (LTE) modulated signals are applied for and digital pre-distortion (DPD) to evaluate its linearization performance. And lower than −46 dBc adjacent leak power ratio (ACLR) can be achieved at 3.5 GHz.

In this paper, a phase shift parameter is introduced to the current waveform of the series of continuous inverse modes (SCIMs) to generate complex fundamental and harmonic admittances. The extended design space based on this novel theory can offer alternative solutions for realizing broadband high-efficiency PAs. To verify the method mentioned above, a 0.9–2.1 GHz PA is designed and fabricated. Experimental results show the PA is able to achieve 63.3%–72.1% drain efficiency and 39.9–41.2 dBm saturated output power in the target band.

A novel energy-efficient hybrid multi-bit Sigma-Delta modulator with a reusable successive approximation register (SAR) quantizer is proposed. By reusing the SAR quantizer, sampling capacitors in the first integrator of the modulator could be eliminated and almost rail to rail input signal range could be achieved by the modulator without the requirement of a high-swing analog adder in front of the quantizer, which is usually power hungry in multi-bit modulators. In this way, small capacitors could be used to meet the thermal noise requirements, thus reducing the power and area consumption. With an improved switching procedure, only a half number of the unit capacitors are needed in the SAR quantizer, which further reduce the area consumption.

Pre-bond TSV test plays a vital role in improving the yield and reducing the cost of 3D ICs. In this paper, a non-invasive solution for pre-bond TSV test based on pulse shrinking is proposed. This method makes use of the fact that defects in TSV lead to variation in the propagation delay - the rise and fall times are first transformed into pulse width, and the pulse shrinking technique is used to digitize the pulse width into a digital code which is then compared with an expected value for a fault-free TSV. Experiments on TSV defect detection are carried out using HSPICE simulations with realistic models for 45 nm CMOS technology. Experimental results show that the proposed method can detect not only open (leakage) fault but also dual faults with high resolution.

A low-voltage inverter-based sigma-delta modulator (SDM) based on a three-phase clock technique is presented. The three-phase clock is proposed to mitigate a performance degradation due to a gate leakage current in advanced process nodes, which reduces noise introduced by the charge injection at the end of a sampling phase and an integrating phase. Simulation results in a 65 nm CMOS process show that the spectrum characteristics of the SDM match well the MATLAB model and achieve 5.1-dB enhancement in the signal-to-noise and distortion ratio performance compared to a traditional inverter-based SDM implementing the uniform loop filter and the same oversampling ratio.

This letter presents the current-gain and high-frequency characteristics of double heterojunction bipolar transistors (DHBTs) consisting of an n-InGaP emitter, a p-GaAsSb/p-InGaAsSb base, and an n-InP collector. The impact of the thickness of the first base metal (Pt) on the base contact resistivity is investigated in a p-GaAsSb/p-InGaAsSb test structure for the purpose of improving f_max. A low base contact resistivity (4.8 Ωµm²) is obtained when the Pt layer is thinner than the p-GaAsSb layer. A fabricated InGaP/GaAsSb/InGaAsSb DHBT with a 0.25-µm emitter exhibits a high current gain of 33 even though the base sheet resistance is as low as 1025 Ω/sq. The DHBT also exhibits an f_max of 703 GHz and a breakdown voltage of 5.4 V. These results demonstrate that this DHBT technology is useful for fabricating high-speed integrated circuits with high output voltages.