A LED driver with a high Power Factor (PF) under universal AC voltage input is investigated in this paper. The AC/DC buck converter with novel dual sampling loop feedback control is adopted to implement the LED driver application. When the main switch is on interval, the control loop does peak current sampling. When main switch is off interval, the control loop does average current sampling. Two control sampling loops are superimposed to regulate the main switch to adapt the AC input voltage and load alteration. Such a scheme can keep the characteristic of peak current control of fast response and avoid the control delay to bring about over current for damage LED. Compared with the conventional peak current control method, the proposed design does not need zero current detect winding and multiplier. Therefore, the circuit architecture of the proposed driver is cheaper. The proposed driver is applied to a 12W LED to analyze the operational principles and verify the practicality.
This paper presents a dc-link capacitor reduction method with P-MOS integrated control method. When compared with SCR chopping method, this novel method can easily integrate the auxiliary switch and control function circuits into one simple chip. Furthermore, the P-MOS control ground can be directly connected onto bus ground. This connection method is convenient to integration and easy drive. The theoretical analysis and detailed control method is given. Furthermore, one ultra-high efficiency GaN-based 65W prototype is made to verify it. The results show that with 27uF*4 bulk caps and integration control method, efficiency can achieve 93.4% at 90VAC with the PCB size 44*31*31mm, 42.3cc under the same dc-link capacitance. Dynamic and EMI performance are also verified. This method is suitable to commercial controller integration for ultra-density and high-efficiency type-c power delivery (PD) applications.
Quantization is a well-known method for deep neural networks (DNNs) compression and acceleration. In this work, we propose the Sample-Wise Dynamic Precision (SWDP) quantization scheme, which can switch the bit-width of weights and activations in the model according to the task difficulty of input samples at runtime. Using low-precision networks for easy input images brings advantages in terms of computational and energy efficiency. We also propose an adaptive hardware design for the efficient implementation of our SWDP networks. The experimental results on various networks and datasets demonstrate that our SWDP achieves an average of 3.3× speedup and 3.0× energy saving over the bit-level dynamically composable architecture BitFusion.
The physical unclonable function based on ring oscillator (RO PUF) is a traditional design suitable for FPGA implementation, but such designs have the disadvantage of low hardware efficiency. This article proposes a new FPGA-based ring oscillator PUF, called loop delay configurable (LDC) PUF. The construction of LDC PUF relies on configurable delay units (CDUs). An LDC PUF configured with n CDUs can generate 2n-1(2n-1) response bits. Additionally, we apply the programmable delay lines technology to enhance the reliability of LDC PUF. Compared with the traditional RO PUFs, the LDC PUF has good uniqueness (48.52%) and reliability (96.91%), and most importantly, it has ultra-low hardware cost.
A high-speed gate driver circuit which can meet both GaN FET and SiC MOSFET is presented. High-speed output drive circuit with wide output drive voltage is introduced in the driver circuit to improve speed and efficiency. By using high-speed level shift circuit and floating step-down low dropout regulator (LDO) circuit, the signal amplitude of the internal circuit for the output drive circuit is reduced, and the speed is greatly improved. Based on the proposed output drive circuit, a galvanically isolated 20MHz 4A gate driver using capacitive coupling with 5.5V to 24V output drive voltage is design and implemented in 180nm BCD process. Test results show the prototype gate driver achieves the rise and fall time of 2.2ns and 2.5ns respectively under 5.5V supply for GaN FET driving, and the rise and fall time of 4.1ns and 4.6ns respectively under 24V supply for SiC MOSFET driving with 20 MHz frequency.
This study provides a theoretical basis and technical guidance for the design of fully differential dynamic comparators to make the offset insensitive to common-mode mismatch. A fully differential dynamic comparator with complementary inputs is proposed. And a metric called Common-Mode Mismatch to Imbalance Ratio (CMMIR) is also presented for evaluating how much the common-mode mismatch affects the offset. Simulation results indicate that the CMMIR of the proposed comparator has a reduction from 2 to 0.1845 with a 100mV common-mode mismatch relative to the CMMIR of conventional ones.
In this paper, a snapback-free and fast-switching SOI LIGBT with three electron extracting channels (TEC) is proposed and investigated. Compared with SBM LIGBT, the trench gate of n-MOS is changed to a planar gate, and a P- region is added to prevent N+ short circuit while providing electron extracting channel. Simulation results show that TEC decreases EOFF by 15% at VON=1.8V relative to SBM when all three channels are open, while TEC still decreases EOFF by 10% at VON =1.55V relative to SBM when only two channels are available. The device achieves the same breakdown voltage level of 603V as SBM without additional trench etch process required.
A K-band CMOS broadband low noise amplifier (LNA) based on the magnetically coupled resonator (MCR) matching network technique is presented and implemented in 0.13-µm CMOS technology. Such LNA consists of two common-source (CS) pseudo-differential stages, which use the capacitive neutralization technique to enhance the inversion isolation and Gain. The MCR-based input matching network achieves good balance and loss performance by inventing a compensated capacitor and series resistor loaded at the center point of the transformer’s second coil, which improves the linearity and Noise Figure (NF) of the LNA. The measurement NF is 3.7-5.6dB within the frequency range of 20.9-26.2GHz (BW3dB), and the peak gain is 18.8dB. The measured IP1dB is -13dBm at 24GHz with a power consumption of 18mW under 1.2V supply.