In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.
In this paper, a novel resistive random access memory (ReRAM) based accelerator is proposed for convolution neural network (CNN) inference accelerations. In ReRAM-based CNN computation, weight parameters can be pre-programmed in ReRAM crossbar arrays, and activations are generated by processing the multiplication-and-accumulation (MAC) operations in the ReRAM crossbar arrays. However, prior works cannot reuse activations in computation, in which the activation dominates the data movements and raises significant energy cost. To deal with this dilemma, a tiling-based dataflow is proposed to enable activation reuse among adjacent ReRAM crossbar arrays to reduce the activation movements. We then develop a ReRAM-based CNN accelerator that can well suit the dataflow to reduce the cost of ReRAM access. Evaluation results show that the proposed design achieves 1.8× energy saving and 2.8× bandwidth saving compared with a state-of-the-art PipeLayer accelerator.
A fully integrated visible light communication (VLC) receiver is presented in this paper. The proposed VLC receiver chip is designed for free-space communication. Utilizing a laser diode as light source, the measured −3 dB bandwidth of receiver is 420 MHz over 0.5 m distance without lens. The integrated receiver is manufactured in an UMC 0.18 µm CMOS process, and the chip area is 889 × 570 µm2. This receiver chip can be used in VLC systems with the following advantages: suitable for VLC free-space channel, low requirements for focusing and alignment, low cost, low power-consumption, compatible with standard CMOS technology, and high integration-density.
Modulated wideband converter (MWC) is a multi-branch structure for sub-Nyquist sampling the signals which spectra are sparse. With several band-limited sampling sequences, MWC can recover the signals by compressed sensing (CS) reconstruction algorithms. However, for hardware-implemented MWC, the hardware scale and imperfection of the physical devices lead to strong column correlations of the sensing matrix which may invalidate the classic CS algorithms. Combined with the characteristics of the sensing matrix of the CS receiver, this paper proposes the double screening orthogonal matching pursuit algorithm (DSOMP) to solve this problem. DSOMP updates the support based on the distance from the residual to the column vector subspace of the sensing matrix and adds a secondary screening mechanism to remove strong interference terms. With the strong column correlation sensing matrix of the CS receiver, DSOMP exhibits an excellent support set recovery rate.
In this letter, a continuous conduction mode boost converter with fast and efficient maximum power point tracking (MPPT) is presented for energy harvesting application. A novel current conservation technique is utilized to sample open-circuit voltage of energy harvesting device without any unnecessary power loss during MPPT operation. Fabricated in 0.35 µm CMOS process, the proposed converter achieves a sampling and tracking time of 80 ns for MPPT. Also, the converter has a peak tracking efficiency of 97.2% and a peak power conversion efficiency of 84.8% with 3-V output voltage.
This paper proposes a new maximum power point tracking (MPPT) control strategy, including a boost converter temporary stopped running (TSR) strategy and an advanced three-point weight comparison method (ATPWC). The proposed ATPWC was used to detect three power points of a photovoltaic (PV) module output, and a microcontroller unit (MCU) was used to calculate the slope of the three power points and to perform MPPT so as to improve the system’s conversion efficiency. The proposed method was successfully applied to an independent solar power generation system, in which the PV module was connected to a boost converter and then connected in series with an inverter to a single-phase 110 VAC/60 Hz output and connected to the power grid. The measured results showed that, in terms of the TSR control strategy, when the system output met a load of 110 Vrms, TSR could reduce switching loss and conduction loss and result in a 10% higher overall system conversion efficiency than that of traditional control. In terms of the MPPT algorithm, actual measurements were carried out under an irradiance level of 100 W/m2∼700 W/m2. Versus traditional hill climbing (HC) algorithm, the efficiency of the proposed ATPWC was better.
This paper proposes a simple method for designing a broadband Doherty power amplifier. The two-port network is used to represent the output matching networks and load modulation networks. Then, the relationships between the parameters of the two-port network and the output impedances of the transistors and the impedances of the power amplifier branches at the combiner are derived. The output matching network and the load modulation network are designed based on the parameters of the two-port network. A broadband Doherty power amplifier is designed and fabricated to verify the effectiveness of the proposed method. The measured results show that the saturated output power is 43.5–45 dBm and the saturated drain efficiency is 65–75% in 2.1–2.7 GHz. And the drain efficiency is greater than 40% at the 6 dB power back-off in the same frequency band. And the gain is above 12 dB.
Current research in selectively supplying power to multi-receiving coil by each means has advantages and disadvantages. In response, the authors designed a more efficient selective power transmission and power allocation method. Multiple different specifications coaxial decoupling coils as the receiving coils. And the transmitting coils of the same specification as the receiving coils are integrally arranged on the same axis. Since the cross-coupling between the receiver coils can be eliminated. Therefore, excite the transmit coil can selectively supply power to the same specification receiver coil. And the load power can be designed by the impedance inverter of the receiving coil.
This letter describes a single-pole six-throw (SP6T) antenna switch in a 180 nm silicon-on-insulator (SOI) CMOS technology for receive diversity and LTE transmit/receive applications. Using a new diode biasing method, the conventional biasing resistor and supply voltage are removed at the body of the stacked-FET switch, a diode is used to connect the body and gate for body bias instead. The biasing diode turns off and on and functions as a high and small resistor for the on and off state. The proposed design helps to achieve low loss and high linearity. The measured insertion loss (IL) at 0.9 and 1.9 GHz are roughly 0.29 and 0.46 dB, respectively. The switch shows a second harmonic of −86 and −83 dBc, and third harmonic power of −94 and −87 dBc with a +26 dBm input power at 0.9 and 1.9 GHz, respectively.