IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 21
Showing 1-8 articles out of 8 articles from the selected issue
LETTER
  • Toshifumi Moriyama, Lorenzo Poli, Paolo Rocca
    Type: LETTER
    Subject area: Electromagnetic theory
    2014 Volume 11 Issue 21 Pages 20140785
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: September 18, 2014
    JOURNALS FREE ACCESS
    The nulling of interferences or jammers impinging on a planar antenna array is addressed by means of an efficient adaptive control strategy based on a Genetic Algorithm. Each element of the array is uniformly weighted and the nulling feature is yielded by controlling a set of radio-frequency switches that connect or disconnect the elements from the beam forming network. Under the assumption that the direction of arrival of the desired signal is known, the on/off setup of the array elements is optimized to maximize the ratio between the power of the desired signal and the total power collected by the antenna array. Representative results concerned with different interfering scenarios with multiple undesired signals are reported to assess the effectiveness of the approach.
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  • Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 21 Pages 20140800
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 23, 2014
    JOURNALS FREE ACCESS
    A novel bit-interleaved coded modulation with iterative detection and decoding (BICM-IDD) receiver for multiple-input and multiple-output (MIMO) systems using Max-Log-MAP algorithm is proposed. This receiver improves the detection and decoding performance by an improved turbo principle, in which pre-scaling the input information of the detector is performed at each iteration. From an information theory perspective, the proposed scheme is proved to outperform the traditional iterative architecture. Simulations results show that the proposed receiver significantly reduces the performance loss incurred by the suboptimal Max-Log-MAP detection and decoding algorithm with small additional complexity.
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  • Yong-Sung Ahn, Taek-Joon Ahn, Kyongsu Lee, Jin-Ku Kang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 21 Pages 20140837
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 17, 2014
    JOURNALS FREE ACCESS
    Noise frequency interference avoidance (NFIA) using binary phase pulse driving and correlated double sampling (CDS) circuit technique is applied to avoid the interference of noise signal in capacitive touch screen panel (TSP). The proposed analog front-end circuitry is composed of a charge transfer circuit and a two-stage cascaded CDS circuit. The purpose of the two-stage cascaded CDS circuit is to remove harmonic noise frequencies interfering with touched data in TSP. If the system detects that noise frequencies interfere with the touched data, the proposed NFIA technique can be applied. Our proposed methodology is implemented in a real TSP system using 0.13-µm CMOS process and the measured SNR is 46 dB with the scan rate of 120 Hz in 21.5 inch TSP.
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  • Toshifumi Moriyama, Makoto Satake
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 21 Pages 20140839
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 21, 2014
    JOURNALS FREE ACCESS
    In this letter, the phase compensation method to remove an interfering phase in Pi-SAR-X2 POLSAR data is proposed. This phase is induced when a steep surface is observed by the H and V polarization antennas which are vertically placed. The proposed method removes the phase errors by using the elevation data which is acquired with the slave-V antenna displaced in the cross-track direction (for interferometric observation). The experimental results show the usefulness of the proposed method.
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  • Ching-Ming Lai
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 21 Pages 20140852
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 23, 2014
    JOURNALS FREE ACCESS
    A conventional battery-powered AC uninterruptible power supply (AC-UPS) that steps up low DC voltage to high DC voltage and cascades with the high frequency inverter is complicated in control and of low efficiency due to two-stage power conversion. This paper presents a three-phase high step-up converter with a single-stage DC/DC power conversion suitable for micro DC-UPS applications. In this paper, the circuit operating theory and steady-state analysis of the proposed topology are first addressed then a 100 V/110 W circuit prototype is designed, built and applied in 24 V-battery-powered micro DC-UPS for a 19 V/85 W laptop PC appliance. The feasibility and effectiveness of the proposed converter topology are confirmed with experimental results. The maximum conversion efficiency of the proposed converter is about 93.5%, and the overall efficiency of the designed system is high due to the losses in the power conversion process when reduced. Compared with the conventional AC-UPS, the proposed micro DC-UPS achieves potentially about 3% maximum energy savings.
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  • C. M. R. Prabhu, Ajay Kumar Singh
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 21 Pages 20140913
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 23, 2014
    JOURNALS FREE ACCESS
    Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation. In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance. A new write mechanism is proposed to reduce the charging/discharging activity on the respective bit lines. The cell is simulated in terms of power, delay and static noise margin (SNM). The simulated results show that write and read power of the proposed LPR cell are reduced up to 78% and 50% at 0.7 V (in 65 nm technology) respectively compared to the 6T cell. The proposed design achieves 2.4× higher read static noise margin (SNM) than the 6T cell.
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  • Nozomi Haga, Kuniyuki Motojima, Mitsuru Shinagawa, Yuichi Kado
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 21 Pages 20140920
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 21, 2014
    JOURNALS FREE ACCESS
    In the development of intrabody communication systems, the most challenging goal is to protect against noise due to other electronic devices. In this regard, it is known that fluorescent lamps using high-frequency electronic ballasts generate significant noise in electromagnetic fields. In this paper, we conduct an experiment of noise voltage received by a wearable transceiver in the presence of fluorescent lamps using high-frequency electronic ballasts, and show that the noise electric fields generated by the lamps result in a significant level of the received noise voltage.
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  • Yue Yin, Yiqi Zhuang, Gang Jin, Xiaoqiang Fan, Xiaofei Qi, Xin Xiang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 21 Pages 20140940
    Published: 2014
    Released: November 10, 2014
    [Advance publication] Released: October 17, 2014
    JOURNALS FREE ACCESS
    A novel circuit architecture for programmable gain amplifier (PGA) is proposed, which simplifies and improves the conventional one and achieves wide precise digital decibel (dB)-linear gain control while obtaining a smaller gain error, smaller chip area and wider bandwidth with low power consumption. In the 0.18-µm CMOS process, the proposed PGA occupies less than 0.09 mm2 of chip area. From the measurements, the PGA shows a dB-linear gain range of 48 dB (−20 to 28 dB) with a gain error of less than 0.18 dB, a gain step of 0.86 dB, a maximum 1-dB compression point (IP1dB) of 10.4 dBm, and a 3-dB bandwidth of 450 MHz at the maximum gain while consuming only 5.8 mA from a 1.8-V supply.
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