A displaying technique of real 3D dynamic images inside a transparent liquid is demonstrated for the first time. Images were formed by micro-flashes generated by means of laser breakdown in liquid. Amongst several types of liquid tested, tap water was found to be an optimal medium for the displaying due to its lowest breakdown threshold power. Electronic color filter was exploited for dynamic coloring of flashes in synchronization with 3D steering of laser beam's focal point.
Due to the extremely short pulse duration, ultra wideband (UWB) signals entail long impulse responses that cause severe intersymbol interference (ISI).In this paper, we propose a low-complexity equalizer based on the minimum bit error rate (MBER) criterion for ISI mitigation in realistic UWB channels. Results showed that the proposed equalizer with shorter filter length and same level of complexity can achieve better performance as compared to equalizers based on the minimum mean square error (MMSE) criterion.
Tunneling Dielectric Thin-Film Transistor (TDTFT), which was proposed to reduce the gate-off current by utilizing a tunneling effect, was fabricated in a bottom-gate structure. For the tunneling dielectric, a 1.7-nm-thick SiNx film was deposited onto the source and drain by a low-pressure chemical vapor deposition (LPCVD) method. The gate-off current of the TDTFT was reduced less than 1/10 in comparison with a conventional TFT. Although the subthreshold characteristics and the gm were degraded due to the tunnel resistance, it will be compensated by further thinning of SiNx film or using the material with the barrier height lower than SiNx.
If resource constraints are specified, the false loop free circuit must be built during the scheduling phase. Although the previous approach guarantees to have a false loop free circuit mapping, it does not attempt to minimize the number of control steps. In this paper, we present an effective approach to find a scheduled code, which not only guarantees to have a false loop free circuit mapping but also to minimize the number of control steps. Experimental results show that our approach achieves good results in terms of the number of control steps.
We developed a method which allows us to fabricate suspended metallic structures without the need for a sacrificial layer. It consists in the selective dip-coating of a low melting point alloy on etched silicon patterns. The technique was applied to the fabrication of a passive one-shot micro-valve sensitive to the ambient temperature and the input pressure. The working principle of the valve was validated. The primary advantage of the system is its low opening pressure difference (a few to tens of kilopascal).
In this paper, we propose an efficient scalable and flexible arithmetic unit which executes word-based multiplication and squaring for RSA arithmetic and addition, multiplication and inversion in GF(2m) for Elliptic Curve Cryptography(ECC) arithmetic operation. The Scalable Word-based Montgomery Modular arithmetic unit (SWMM) can process RSA with modified Finely Integrated Operand Scanning (FIOS) Montgomery algorithm. Also, the proposed flexible hybrid Galois Field Arithmetic Unit (GFAU) is beneficial in cost-effectively implementing ECC operation extensions. The proposed processor is synthesized by employing Synopsys Design Analyzer with a Hynix 0.25 standard cell library at the worst case of 2.3V, 100°C. The synthesis results show that the gate count of processor is below 60,000.
A novel source-injection serial-coupled (SISC) topology for designing LC quadrature voltage-controlled-oscillator (QVCO) is proposed. The proposed topology uses the advantages of the cascode-coupling QVCO and source-injection parallel-coupled (SIPC) QVCO topologies and provides a good phase noise performance with good quadrature phase accuracy. A 1.8GHz, 1.8v designed QVCO based on this topology shows a phase noise of -136dBc/Hz at 1MHz offset frequency thereby showing 5dB and 7.3dB lower phase noise than the SIPC and the cascode-coupling topologies respectively. This result is obtained from the simulation based on 0.18u CMOS technology and on-chip spiral inductor with Q of 8.