IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 17 , Issue 5
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LETTER
  • Koushick Mathur, Palaniandavar Venkateswaran, Rabindranath Nandi
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 5 Pages 20190738
    Published: 2020
    Released: March 10, 2020
    [Advance publication] Released: February 13, 2020
    JOURNALS FREE ACCESS

    A new voltage-variable inductor (VVI)-L realization scheme using composite Current Feedback Amplifier (CFA) and Multiplication Mode Current Conveyor (MMCC) active building block (ABB) is presented. Subsequently a LC-type voltage controlled quadrature oscillator (VCQO) with linear tuning law is derived by replacing the CFA by another MMCC. Experimental results based on PSPICE simulation and hardware circuitry for a linear tuning range of oscillation frequency (fo) ∼9.3 MHz with satisfactory phase-noise figure on the wave generation, had been verified. Effects of the ABB nonidealities are shown to be insignificant.

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  • Yinhang Zhang, Xi Yang
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 5 Pages 20200009
    Published: 2020
    Released: March 10, 2020
    [Advance publication] Released: February 07, 2020
    JOURNALS FREE ACCESS

    This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual inter-symbol interference. The chip area including pads is about 1.2 mm2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

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  • Daiki Kitagata, Shuu’ichirou Yamamoto, Satoshi Sugahara
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 5 Pages 20200032
    Published: 2020
    Released: March 10, 2020
    [Advance publication] Released: February 17, 2020
    JOURNALS FREE ACCESS

    A store energy and latency reduction architecture based on proactive useless data flush (PUDF) is proposed for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs). Prior to the store operation to the MTJs in the array, the PUDF architecture predicts store-unneeded blocks having useless data and shuts down these blocks in advance. As a result, the store energy and latency can be reduced depending on the proportion of store-unneeded blocks, which enhances the energy reduction efficiency of power gating (PG) using the NV-SRAM. The energy and latency characteristics are computationally analysed and experimentally verified using circuit parameters extracted from fabricated test-element-group (TEG) circuits of the NV-SRAM.

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  • Zhao Lei, Zhang Xiaolin, Ji Wenxin
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 5 Pages 20200034
    Published: 2020
    Released: March 10, 2020
    [Advance publication] Released: February 17, 2020
    JOURNALS FREE ACCESS

    A non-binary split-type MOM weighted capacitor array based on fractal geometry for SAR (Successive Approximation Register) ADC is proposed. By taking advantage of the geometric characteristics of the Hilbert curve, the capacitor array avoids the use of complex common-centroid structure and complex wiring. The test results of the SAR ADC using this capacitor array show that, the measured DNL and INL were −0.26/0.38 LSBs and −0.37/0.38 LSBs, respectively. The ENOB is 8.66 bits. The SAR ADC was implemented using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 330 µm × 1190 µm and 1.89 mW, respectively.

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