A CMOS Low Noise Amplifier (LNA) is designed for RF application by using TSMC RF CMOS 0.18µm technology. Noise cancellation technique is applied to cascode transistor of the LNA core; because source parasitic capacitors of this transistor cause the noise figure increases in high frequency. The linearity of LNA is modified by the second order interaction between the PMOS and NMOS transistors in cascode structure. With this topology lower noise figure, improved linearity and lower power dissipation can be attained. This LNA achieved maximum power gain of 15.3dB at 3GHz band, noise figure of lower than 2.5dB over the whole band of 3-5GHz and IIP3 of +10dBm at 3GHz while drawing 7.42mA from 1.8V supply voltage.
This paper presents a continuous-time current comparator with low input impedance enhancing the accuracy of comparison. The proposed circuit employs low impedance common-gate structures as input stages and further uses common-source feedback structures to enable extremely reduction of input impedances. The input impedances are well designed to be balanced, so that the proposed design can be applied to perform precise comparison between two terminals with tiny varied currents. An implemented chip was fabricated by TSMC 0.35µm CMOS process with its input impedances and propagation delay are 66.8Ω, 66.6Ω and 2.5ns respectively while the average power consumption is about 1.64mW.
In this letter, an adaptive equalizer with an inter-symbol interference (ISI) level measurement using a periodic training pattern is presented. The compensation level of the equalizer is determined by measuring ISI level and fed back to the feed-forward equalizer. The proposed algorithm is verified with a 100-cm flexible flat cable (FFC) at 10Gb/s data rate using a 90nm CMOS process technology. Compensation range is from 15dB to 33dB with a tuning range of 18dB, and the current consumption is 7.6mA at 1V power supply.
Pseudorandom number generators (PRNGs) should satisfy two main criteria, high randomness quality and fast computation of a sequence of numbers. In this paper, a comparative study of two-dimensional Cellular Automata (CA) based PRNGs is performed to evaluate the randomness quality and the hardware constraints involved in terms of configuration parameters such as, transition rules, neighborhoods and bit extraction schemes. Experimental results show that CA-based PRNGs present good randomness quality using standard test suites, and they are well suited for parallel implementations in Field Programmable Gate Array (FPGA) technology taking advantage of the on-chip fine-grain and distributed computational resources.
An energy-efficient tri-level switching scheme based on half of the reference voltage (Vref) is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). With respect to the set-and-down switching scheme, the common-mode voltage variation at the input of the comparator reduces. By using Vref/2, the switching energy and the capacitor area are reduced. The proposed scheme achieves 97.26% less switching energy with one forth of the capacitor area as compared to the conventional architecture.
A reconfigurable fully differential programmable linear-phase filter is presented in the paper which can be used in portable multichannel electroencephalogram, electrocardiogram, wireless brain-heart monitoring systems used in hospital or home care settings. To reduce the influence of coefficient sensitivity and maintain an undistorted bio-signal, a fifth-order ladder-type Bessel Transconductance-Capacitor (Gm-C) lowpass filter is employed. The filter is designed as part of on-chip self-adjusting noise suppression block and its programmability makes it suitable for different biomedical signals processing. Simulation results show that this low-voltage and low-power filter possesses the HD3 of 50.7dB, dynamic range of 62dB, dc gain of -2.899dB, and power consumption of 30µW. Meanwhile, the designed filter can effectively reduce self-adjusting noise on specific channels and anti-aliasing of the analog-to-digital converter (ADC).
A tunable metamaterial absorbers (MA) comprised of a new combination shaped metal elements printed on a dielectric substrate loaded with PIN diodes were demonstrated. Through biasing at different voltages to control the diodes, the reflectivity characteristics of the structure can be varied over the entire 2-18GHz range. A qualitative analysis by a simple visualization method is carried out on the parameters of the tunable MA. Both numerical calculations and microwave measurements have verified the performance.
In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floor-planning-directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanning-directed huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.
In this paper, we propose a reconfigurable charge pump (RCP) circuit that could change its architecture according to sunlight variation. In strong sunlight, the RCP works by the parallel mode that can maximize the output current. In moderate sunlight, the RCP changes to the serial-parallel mode. When sunlight becomes weak, the RCP runs by the serial mode to keep its output voltage around the target voltage. Compared with the fixed-mode circuit that maintains the serial mode all the time regardless of sunlight variation, the RCP can generate 2.5 times larger output current and has power efficiency better by 24%, in strong sunlight. The area penalty and overhead in power efficiency of the RCP are only 15.8% and 1.2%.
Addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper a 1-bit full adder cell which uses only six transistors has been proposed. In this design, three multiplexers and one inverter are used to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay and power-delay product (PDP) are analyzed and compared with the existing adders using BSIM4 at 90nm feature size. The results show that the proposed adder has both lower power consumption and low PDP value. The proposed full adder clearly outperforms other existing adders in its temperature sustainability behavior versus power dissipation, leakage current parameters. The low power and low transistor count makes the proposed 6T full adder cell a candidate for power-efficient applications.
This paper presents an innovation and fabrication process of electrical contact structure using reel-to-reel continuous systems in flexible device technology. A coating of poly(3,4-ethylenedioxythiophene) poly(4-styrenesulfonate) as a solid conductive layer deposited on silicone elastomer structures are employed in composing the electrical circuit through a large area of woven electronic textile (e-textile), and functions as the electrical contact between weft and warp (interlaced) fiber ribbons. From the resistance measurements using flexible sheets by weaving PET ribbon cable, the structures enhance the durability, flexibility and stability of electrical contact in the woven e-textile better than those of the ribbons without it.