A method of using Interrupted-Sampling Repeater Jamming (ISRJ) to cancel radar target echo is proposed. After the principles of ISRJ are expounded, three conditions that should be met for radar echo cancellation are proposed, including range synchronization, phase coherent and amplitude match. Then, the restriction for key parameters of ISRJ, i.e. the repeater power, the delay time and frequency of repeater are deduced in theory. At last, the influences of those parameters on radar echo cancellation are discussed in detail. Some numerical results are presented to verify the effectiveness of this method. This work is beneficial to the jamming design and use of ISRJ.
An autonomous self-healing technique utilizing a self-injection-locked Fabry-Perot laser is proposed for optical and wireless seamless communication systems. The proposed technique is more promising than the other techniques because of its high reliability and simple configuration. It has been experimentally confirmed that the self-healing technique can be adopted in optical and wireless communication systems with plural wireless back-up links.
This paper presents dynamic power saving schemes for low power operation in the modem system shared memory architecture of mobile system-on-a-chip (SOC). Different power modes are considered to obtain the minimum power consumption in a modem operation. An electronic system level (ESL) virtual platform is implemented to verify the proposed scheme with real traffic data extracted from the actual phone. Experimental results show that the proposed method reduces the power consumption by 42% and 15% in 2G and 3G respectively.
An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-body-biased 8T cell. Also, a write driver is presented to enable the bit-interleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8 V to 0.3 V (0.2 V when the write wordline is boosted to 0.36 V) and the total power is reduced by four times of magnitude.