This paper presents a new three-phase five-level inverter for direct torque control (DTC) drives application. The advantages of the inverter are reduced output harmonics, switching losses and number of power switches. The multilevel PWM modulation method as well as output voltage analysis based on symmetrical sampling are presented. The proposed inverter is compared with the conventional inverter in terms of its current's total harmonics distortion (THD). Experimental results of DTC drive of permanent magnet synchronous motor (PMSM) are also presented for verification of its proposed function.
In this paper, an experimental analysis of the electrical characteristics of the PTSCR was conducted. The PTSCR contains a high trigger current and a holding voltage that enables latch-up immune during normal operation. The PTSCR in each process technology is verified by the TLP system as well as a hot chuck controller. The experimental results show that the trigger current and holding voltage are higher than that of other SCR devices. At higher temperatures, the holding voltage of the PTSCR decreased due to the operation mechanism of the SCR, while the trigger current increased due to the MOSFET trigger mechanism.
This paper presents a new model for simulation of Electromagnetic Interference (EMI) in power converters. Despite the fact that a Matrix Converter (MC) has been selected, such methodology can be applied to other converter topologies. The EMI model relies on a combination of time and frequency domain techniques in order to not only reduce the computational complexity but also to avoid convergence problems. Common Mode (CM) leakage current, which lays basically in A band (10kHz to 150kHz), is simulated and such results are compared with those obtained from the MC prototype showing a good concordance in terms of peak value.
This paper presents an all-digital on-chip ramp waveform generator for an 8-bit single-slope ADC. The proposed ramp waveform generator consists of static CMOS digital circuits and is designed using standard cells aiming for the process portability. The proposed circuit realizes digitally-controlled ramp output and also realizes two step coarse-fine ramp waveform to speed up the single-slope analog-to-digital conversion. The experimental results of the circuit simulation with random variation on 0.18µm CMOS process demonstrate the feasibility of our ramp waveform generator and 8-bit two-step single-slope ADC with DNL within ±0.2LSB and INL within ±0.8LSB.
This paper aims to design a new transceiver with a signal space diversity (SSD) in layered multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. To this end, a enhanced coordinate interleaver (E-CI) that swaps a random pair of subcarriers is first proposed in order to realize readily the detection ordering required for a layered MIMO processing at the receiver. A enhanced maximum likelihood (E-ML) detection is also proposed in order to provide SSD gain after the MIMO detection processing. The performance of layered MIMO-OFDM system is evaluated and compared with that of MIMO-OFDM systems without the E-CI and E-ML detection over a time-varying Typical Urban (TU) channel.
Work function modulation of PtSi by alloying with Yb to achieve ultra-low contact resistance for advanced CMOS was investigated. PtxYbySi was formed by depositing Pt(6-18nm)/Yb(2-14nm)/n-Si(100) stacked structure followed by 400-800°C/1-30min silicidation in N2 ambient. It was found that barrier height for electron(ΦBn) was decreased as the silicidation temperature and time increased, and ΦBn was reduced to 0.52eV by depositing Pt(6nm)/Yb(14nm) followed by 800°C/30min silicidation. It was found that Yb diffusion toword the silicide/Si interface was enhanced, compared to the sample formed by 500-600°C silicidation, which leads to further decrease of ΦBn. The estimated effective work function of PtSi decreased from 4.92eV to 4.57eV.
A readout method which is suitable for high-density active microelectrode arrays used in electrophysiology experiments is presented. Amplitude modulation of consecutive channels enables simultaneous recording and transmission of the signals recorded on multiple electrodes, using a single amplifier. The physical limitation of the readout method is demonstrated to relate to the summation of the thermal noise of each recorded signal at the input of the amplification stage. Post-layout simulations of a possible circuit implementation in a 0.18µm CMOS technology show that five pixels connected to a single amplifier are feasible with a pitch dimension of 17µm, and an SNR value of 15dB.
To reduce the contact resistance at source/drain regions in scaled CMOS, control of PtSi work function by alloying with Hf was investigated. Pt(10-20nm)/Hf(0-10nm)/n-Si(100) stacked layers were annealed at 400°C/60min in a flowing N2 ambient to form silicide layer. In the case of alloying with 3-6nm-thick Hf, it was found that barrier height (ΦBn) for electron was linearly reduced from 0.84eV to 0.56eV with Hf thickness in the initial stacked layer, which corresponds to the work function of 4.89eV and 4.61eV, respectively. Furthermore, the reduction of ΦBn could be precisely controlled by 94meV/nm with Hf thickness.