FPGA overlay technologies have been introduced to provide inter-FPGA bitstream compatibility by implementing virtual FPGA (vFPGA) layers on physical devices. Conventional LUT-based fine-grained vFPGAs have very large resource overheads. In this paper, we propose a fine-grained vFPGA overlay architecture that employs our previously proposed scalable logic module (SLM) as a logic cell. SLMs can cover most frequently used logics with far fewer hardware resources than LUTs. Evaluation results show that a 7-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 32% and 35% on an Artix-7 FPGA, 30% and 35% on a Kintex-7 FPGA, and 30% and 35% on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size.
Due to the uncertainties from manufacturing processes and material properties, MEMS (micro-electro-mechanical system) microphone may exhibit significant variations in their performance compared to the nominal design. The published analytical methods have obvious shortcoming, which cannot meet the needs of both accuracy and efficiency. In order to improve efficiency, the MC (Monte Carlo) simulation based on ANN (artificial neural network) is presented to analyze the uncertainty of sensitivity of polysilicon circular clamped diaphragm microphone. Using the PDS (probabilistic design system) of Ansys software and MC simulation to predict the qualified rate of microphone, the simulated results are 91.2% and 91.4% respectively. The qualified rate of manufactured microphones is 91.5%. In addition, the time-consuming of these two simulations are 10 minutes and about 3000 minutes. This paper also analyzes the change of sensitivity probability densities with the varieties of nominal parameters of diaphragm. The results show that the presented MC simulation with accuracy and high efficiency is an alternative to the traditional methods.
High-intensity focused ultrasound (HIFU) has been confirmed to be useful for cancer treatment. However, the miniaturization of traditional impedance matching networks for HIFU has limitations. In this paper, a time-division multiplex auto-impedance matching network is proposed for Class D power amplifiers used in HIFU systems to improve performance and reduce the system size. A comparison with previous articles shows that the proposed system can automatically compensate for the impedance drifting of five-channel transducers caused by temperature variations or manufacture tolerance. The operating frequency of the circuit is 1.25 MHz, and the power consumption is 416 mW.
A novel reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed. It features a built-in thyristor formed by introducing a floating P-well surrounding an N+ collector. The realization of the thyristor barely increases chip area or complicates fabrication. It helps to realize the RC function and prevents the device from working in the unipolar mode, which eliminates the snapback problem. Moreover, since the thyristor provides an electron extraction path during the turn-off operation, the switching performance is improved. Simulation results show that, compared with the conventional LIGBT with an antiparallel diode, the proposed device presents the reverse recovery charge (Qrr) and the turn-off loss (Eoff) reduced by more than 30%, and the RC voltage drop (VF) decreased by about 0.1 V.
This work presents a novel concept of antenna-and-pulse-generator codesign for realizing FCC-regulation-compliant IR-UWB transmitters. The method contributes to a compact design that significantly reduces the overall device footprint and energy consumption. A Gaussian mono-pulse generator and a folded-dipole antenna with a bandwidth of 7.8–9.5 GHz are co-optimized, eliminating any matching sections. The energy consumption for each impulse emission is only 2.6 pJ and 100 Mpulse/s operation of the transmitter complies with the FCC mask. The transmitter of this kind shows promise for size-restricted and ultra-low power applications such as medical implants.
Physical unclonable function (PUF) is a reliable physical security primitive. The Weak PUF and Strong PUF are two well-known PUF topologies. Strong PUF can be used to authenticate and protect intellectual property on FPGA chips. Classic PUF designs, like arbiter PUF, are hard to implement on FPGA and severely threatened by the machine learning based modeling attacks. In this work, we propose a new Strong PUF on FPGA by combining Weak PUF with obfuscation logic. Experiment results on a 28 nm FPGA show that the resistance to modeling attack is good and the hardware overhead is small.