We present recent progress and challenges toward ultrahigh-speed optical time-division multiplexed (OTDM) transmission with a single-channel bit rate beyond 10 Tbit/s using optical Nyquist pulses. First, we review the technological progress made on OTDM/ETDM and digital coherent transmission over the last 20 years and highlight the challenges that must be met to achieve a higher bit rate and a higher spectral efficiency. We then present our proposed scheme that consists of an optical Nyquist pulse and its OTDM transmission and show that coherent Nyquist pulses are very attractive in terms of realizing an extremely high bit rate and high spectral efficiency simultaneously. We describe our recent demonstrations of a single-channel 10.2 Tbit/s (2.56 Tbaud) DQPSK transmission over 300 km using non-coherent Nyquist pulses, and a 15.3 Tbit/s (1.28 Tbaud) 64 QAM transmission over 160 km using coherent Nyquist pulses, in which the highest bit rate we achieved was 15.3 Tbit/s with a spectral efficiency as high as 8.7 bit/s/Hz. We also present a 12.8 Tbit/s (1.28 Tbit/s/ch × 10 ch) transmission of 320 Gbaud DQPSK Nyquist pulses over 1500 km. These results indicate that Nyquist pulses are advantageous not only for achieving an extremely high bit rate but also for realizing a WDM transmission with a 1 Tbit/s channel capacity over long distances.

A CMOS image sensor physical unclonable function (CIS PUF), which generates a unique response extracted from manufacturing process variations, is utilized for device authentication. In this paper, we report modeling attacks on a CIS PUF, in which column fixed pattern noise is exploited in a sorting attack. When the PUF response is generated with a pairwise comparison method, unknown responses are predicted with an accuracy of over 87.8% with only 0.31% of the training sample of the entire challenge and response pairs.

Caching the updated parity chunks in the RAID buffer can absorb update operations on parity chunks of data stripes in RAID-enable SSDs. Thus, the negative effects of write penalty can be minimized. However, caching integrated parity chunks fails to efficiently use the capacity-limited RAID buffer, as sometimes a major parts of parity chunk are not modified comparing with the parity chunk saved in SSD blocks. This paper presents a patch-based cache management scheme on parity chunks, for improving cache use efficiency of RAID-enabled SSDs. Specifically, it only caches the modified portions of parity chunks in the buffer(called paritypatches), which are corresponding to the updated parts of data chunks in the same stripe. Through a series of simulation tests on several disk traces, we illustrate our proposal can noticeably reduce the I/O latency by between 12.2% and 17.1%and the number of block erases by 20.8% on average, in contrast to state-of-the-art approaches. In brief, our proposed cache management scheme can work in RAID-enabled SSDs to achieve better I/O performance and extend the lifespan of SSDs.

This study introduces a new bootstrapped switch for improving sampling linearity. In this technology, the introduction of a negative-voltage bootstrap capacitor reduces the parasitic capacitance at the critical signal node, thus improving its linearity. The proposed circuit is simulated using 0.18-µm complementary metal-oxide-semiconductor technology. The parasitic capacitance of the proposed scheme is approximately 30% lower than that of the conventional structure. In the case of rail-to-rail input, the proposed switch achieves a signal-to-noise-plus-distortion ratio (SNDR) of 83.3dB and a spurious-free dynamic range (SFDR) of 82.3dB from a 1.2-V supply at a 50-MHz sampling rate. The SFDR and SNDR of the proposed bootstrapped switch increase by 11.7 and 12.7dB, respectively, compared with those of conventional bootstrapped switches.

This letter proposes a simple method for designing broadband high-efficiency power amplifiers (PAs). Hybrid Class EFJ PAs theory is applied to achieve both high-efficiency and broadband at the same time. In order to make it more practical, a low-pass filter structure is introduced to design output matching circuits that satisfy the impedance conditions of Class EFJ PAs. Moreover, this paper exploits the characteristics of the transistor’s output impedance, and selects three frequency points to design and synthesize a low-pass matching network. For validation, a PA working in 1.3-3.9GHz is designed and fabricated based on CGH40010F transistor. The measurements illustrate that output power is from 40.5dBm to 42.3dBm and drain efficiency is between 61.3% and 71.2% at saturated level in the target frequency band. The ACLR is smaller than -28.4dBc in the same frequency band.

In this paper, a high-efficient and low-cost secure AMBA framework utilizing the bus data encryption modeling is proposed to resist the probe attacks. By encrypting the confidential data flowing through the bus, the proposed configurable encryption model meets the security requirement of total SoC. Further, a data encryption pipeline with the third-level branch predictor is proposed to accelerate the encryption process. Finally, an SoC with the 32-bit proposed AMBA framework is established and validated with 55nm technology. Experimental results show that the proposed framework achieves 6152Mbps throughput, consumes 39547um² area, and provides a stronger resistance compared to the other countermeasures.