This paper proposes a random shifting data weighted averaging (RSDWA) algorithm where a bidirectional circular shift register is co-worked with a pseudo-random sequencer to form a random module, which makes mismatch error suppressed in the frequency domain, therefore it can achieve a higher Spurious Free Dynamic Range (SFDR) compared with the traditional DWA. To verify the proposed algorithm, a 6-bit Nyquist-rate resistor ladder DAC is designed based on 180nm CMOS process. The simulation results show that the proposed RSDWA can increase SFDR by 7.3dBc and decrease the Integral Non-Linearity (INL) from 0.75LSB to 0.37LSB compared with the traditional DWA algorithm.

In order to further suppress the chattering problem of permanent magnet synchronous motor (PMSM) speed control system, a fuzzy sliding mode speed controller based on particle swarm optimization algorithm was proposed on the basis of exponential reaching law Sliding mode control (SMC). This method first uses Particle Swarm Optimization (PSO) to preliminarily tune and optimize the sliding mode parameters; Then, a new exponential approach law is designed, which introduces system state variables and fractional polynomials containing exponential terms in the constant velocity term of the exponential approach law to accelerate system convergence speed and reduce overshoot; Finally, fuzzy control is used to dynamically adjust the constant velocity term parameters, further improving system performance. The simulation results show that the fuzzy Sliding mode control based on PSO has better response performance than the exponential approach law Sliding mode control. The overshoot and speed fluctuation are reduced by 18.96% and 0.8r/min respectively, and the chattering suppression ability and dynamic performance are improved.

In integrated designs of multiple IP cores across clock domains, signal metastability can occur due to unequal wiring and variations in PVT. This leads to inconsistency between the signals obtained by the target and the signals at the source. Establishing a FIFO is one of the crucial methods for addressing data inconsistency. Therefore, this paper proposes a novel array structure based on one-hot coding, where the row and column codes generated by Johnson counters are XORed to create the address pointer. This innovation reduces the area for the FIFO and enables rapid control logic using one-hot coding. Furthermore, a state-based approach is employed to mitigate the impact of memory size on the empty/full detection circuit. It only records the read-and-write addresses, enhancing the reconfigurability of the FIFO. Using the SMIC 0.18µm process, the synthesis and simulation results demonstrate that the FIFO can achieve a maximum operating frequency of 830MHz. Additionally, compared to similar synchronous FIFO, it exhibits a significant 30% reduction in area. When considering different FIFO depths and widths, the method proposed in the paper shows an area reduction of 30% to 47% compared to similar synchronous methods. For a depth of 16 and a data width of one word, the power consumption is about 6.8 mW. The FIFO presented in this paper can serve as a reference for data transmission between different clock domains.

This paper presents a 20.8-23.2GHz integer-N sub-sampling phase-locked loop (SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage controlled oscillator (VCO) is employed and its output is feedback as the input to SSPD in sub-sampling PLL to reduce the reference spur without requiring extra area and power consumption. In addition, a common source feedback circuit is adopted in the proposed sub-sampling charge pump (SSCP) to reduce current mismatch. The proposed sub-sampling PLL is implemented in a 40nm CMOS technology, measured results exhibit a frequency tuning range of 10.9% from 20.8 to 23.2GHz. The measured phase noise is -106.92@1MHz offset, the reference spur is -47.05dBc. The typical power consumption is 29.1mW from a 1.1V supply voltage, leading to a PLL FoM of -245.9dB. The PLL occupies a core area of 1.2mm².

A compact 4-channel 224Gb/s PAM4 optical transmitter in 130-nm SiGe BiCMOS technology is presented employing 3-tap feedforward equalizer (FFE) and continuous time linear equalizer (CLTE) techniques. One pre-emphasis tap and CLTE structures broadened the bandwidth to 26GHz. Moreover, the peak-peak value of group delay for this system is reduced to 6.7ps by adopting one pre-fall tap structure. The output stage employs current mode logic circuits to achieve high modulation currents. This chip occupies an area of 1.8mm×1.95mm with a 250um channel pitch. An operating rate of 56Gb/s/ch is achieved when inputting 28Gbaud PAM-4 signal. The single-ended output voltage amplitude is 240mV, corresponding to 5.6mA modulation currents.