An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor’s series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.
This study presents a new structure of vertical-type CMOS Hall devices to detect 3-D magnetic field in various types of applications or devices with high sensitivity. For enhancement of sensitivity, a 4-contact structure instead of a conventional 3-contact or 5-contact one is adopted. A prototype of the proposed VHD is fabricated in 0.18 um CMOS process, and the sensitivity increases by 13 times which corresponds to improvement in SNR by 22.3 dB without any additional power or area. The VHD with 4 contacts can be useful in automotive applications where detection of 3-D magnetic field with high resolution is necessary.
In this paper, an envelope detection scheme of single carrier 16-ary quadrature amplitude modulation (16QAM) for Intensity-Modulation/Direct-Detection (IM/DD) radio-over-fiber (RoF) system is theoretically and experimentally investigated. Based on the proposed scheme, the mm-wave 16QAM signal is down-converted to the intermediate frequency (IF) 16QAM one by an envelope detector (ED) and there is no use of a mixer at the user side. We theoretically and experimentally study the performance of the signal under various conditions. In the system, 2 GBaud 16QAM signal is delivered over 25 km standard single mode fiber (SSMF) link and 2.9 m wireless link under bit error rate (BER) of 3.8 × 10−3.
This paper presents a temperature sensor with glucose sensor interface based on configurable incremental sigma delta (ΣΔ) Analog-Digital-Converter (ADC). A current readout circuit is implemented based on the same ΣΔ modulator of the temperature sensor. New dynamic biasing scheme of inverter-based operational transconductance amplifier (OTA) is proposed to improve the settling time of the biasing voltages. This design was fabricated using 0.13 µm CMOS process. Compared with the traditional circuit, this circuit reduced the chip area by 25%. According to the test results, when the temperature changes from 20°C to 50°C, the temperature sensor inaccuracy is ±0.15 °C and the ADC achieves 9.3 effective number of bits (ENOB) with 3 µW power consumption.
An innovative high-precision coarse-fine time-to-digital converter (TDC) is presented. The TDC architecture mainly consists of a coarse counter and a delay-line-based analog-digital hybrid interpolator. In order to improve the precision, the key timing control of the interpolator is provided by a novel customized synchronizer. Comparing to the traditional delay-line-based interpolator, the proposed analog-digital hybrid interpolator using the multi-voltage sampling technique improves the resolution significantly. A prototype chip has been fabricated in a 0.35 µm CMOS process. After the calibration and calculation based on fitting algorithms, the TDC prototype reaches a dynamic range of 512 ns and a single-channel single-shot precision of 6 ps using the external look-up table (LUT) for the interpolator.
This paper presents a wideband (0.07–3 GHz) receiver front-end realized in 65 nm CMOS technology for mobile Software-Defined Radio (SDR) applications. A more power-efficient wideband common-gate low-noise amplifier (LNA) featuring a common-source path for noise-canceling is proposed to trade-off linearity and noise figure (NF). A current commutating down conversion passive mixer with transimpedance amplifier is applied to achieve low flicker noise and high linearity with low supply voltage. Measurements show that the front-end achieves conversion gain higher than 42 dB. The measured NF ranges from 2.28 to 3.68 dB in the covered frequency range and IIP3 varies from 9 to 12 dBm versus different frequencies. The front-end occupies an active area of 0.8 mm2 and consumes a power of 40 mW from 1.2 V supply voltage.
In this paper, a CMOS Image Sensor (CIS) capable for in-pixel selective light detection and background light suppression is presented. The pixel circuit is composed of demodulation transistors and Adaptive Charge Unit (ACU), realizes in-pixel selective-charge-subtraction. Demodulation transistors are used for selective light detection. And ACU is used for background light subtraction to prevent saturation for wide dynamic range. The presented image sensor has been fabricated in 0.18-µm CMOS process and successfully tested, and it has a 64 × 64 pixel array. The minimum signal-to-background ratio (SBR) is −18.8 dB and the dynamic range is 89.3 dB.
Memory system, as the basic constituent of the computing system, has a inevitable impact on the system performance. Traditional bus-based memory access system cannot fulfill the performance requirement of the future high-performance computing system due to its limitation on energy-efficiency. Memory-centric network (MCN) is considered as a promising candidate for future system interconnect. To improve the energy-efficiency of memory access system by utilizing MCN, the topology of MCN needs to be carefully designed, as interconnection links take a huge part of power consumption. In this letter, we propose a new memory network topology named ALPHA. ALPHA is a 2-D topology. As ALPHA employs different types of interconnection links in the X-dimension and the Y-dimension, respectively, it can maintain high throughput while using fewer links. Besides we redesign the switch of HMC for its implementation in ALPHA. We make a comparison between ALPHA and four popular topologies. The simulation results show that ALPHA greatly increases throughput and decreases latency.
The current paper presents an inverter chain with parallel output nodes design for the purpose of eliminating the single-event transient (SET) pulse. The structure of parallel output nodes combined with the layout utilizing isolation approach can eliminate the SET pulse substantially. As compared with the conventional inverter chain as well as the inverter chain of source-isolation approach and the duplicated inverter chains with C-element, the simulation results illustrate that the proposed inverter chain manifests an effective improvement of immunity to SET. With regard to P-hit, the proposed inverter chain is capable of attaining a stable output irrespective of the state of the struck PMOS being OFF or ON. With regard to N-hit, the proposed inverter chain can also maintain the final output steadily. As long as the SET pulse is not generated at the eventual output node, the pulse can be eliminated by the proposed inverter chain. Besides that, the proposed approach is also applicable to the circuits with the structure like inverter chain.
A broadband high efficiency Class-J power amplifier (JPA) with new output impedance calculation method is proposed. A compact low-pass output matching network and an opened-sector microstrip line instead of a parallel capacitor are employed to provide impedance space for broadband design. To enhance the bandwidth, a multi-stage Chebyshev low pass matching network is used with input matching network. For demonstration, a broadband high efficient JPA based on proposed structure is designed and fabricated. Measurement results show that the drain efficiency between 55%–67%, output power from 40 to 42.6 dBm with more than 10 dB gain over a bandwidth of 1.0–3.0 GHz, accounting for 100% fractional bandwidth. When employed by a 5 MHz WCDMA signal with 8-dB peak-to-average power ratio (PAPR), the adjacent channel power ratio (ACPR) between −24.1 and −32.4 dBc without digital predistortion (DPD).
As the most critical components of Network on chip (NoC), the routers need to select suitable output ports and guarantee every flit accesses the hardware resource exclusively. Thus they are normally designed with several pipelines. However, most flits don’t compete for the same output port with other flits in real applications. In this work, we introduce a bypass path to the traditional router thus the non-conflict flits can be forwarded directly. Combined with several other optimizations, we propose a bypass-based low latency NoC router (BNR). When no congestion occurs, BNR can transfer the flit through the bypass path with only one cycle. Otherwise, the flits are transferred through the conventional path with two hops. Besides, we also present a simplified version, BNR-S. Compared with BNR, it only bypasses the short packets and will reduce the area overhead significantly. For the synthetic traffic with different injection rate, BNR achieves 1.48× and 1.31× speedup than the two baselines while BNR-S achieves 1.3× and 1.15×. They also bring obvious benefits for several real applications. In addition, the experiments also illustrate that the proposed bypass mechanism can reduce dynamic power.
We propose a novel all-optical feedforward automatic gain control (AGC) scheme for multicore erbium-doped fiber amplifiers (EDFAs). In this scheme, a semiconductor optical amplifier (SOA) is used in an AGC circuit. The first experimental demonstration of the dynamic gain control operation is reported. A maximum gain difference of ∼0.12 dB is successfully obtained using the control scheme. The proposed AGC circuit using an SOA achieves a significantly small response time constant of less than 5 µs, which is more than 20 times smaller than that of the circuit using an EDFA.
A novel charge pump system with new regulation and clock generating techniques is proposed and verified in a 0.13 µm CMOS process. Rather than generating the reference voltage by band-gap reference (BGR) and the detected voltage by high voltage divider in the conventional regulation, both voltage reference and division of proposed pump system are implemented by single new circuit. Besides, the conventional oscillator for clock input of charge pump system is removed while an adaptive clock generation scheme is introduced to reduce the power consumption and shrink the system size. The experiment results show that the pump system can produce a stable and smooth output with a small ripple, and the high output accuracy is comparable to the conventional solution equipped with BGR. Moreover, the power consumption of the pump controlling is reduced by about 80% while the size of pump system is decreased by about 25%. Therefore, the proposed regulated charge pump (RCP) is very suitable for ultra-low power and high precision applications, for example, the embedded nonvolatile memories (eNVMs).
The traditional SSHI circuit forms a resonant loop to salvage the charges that would otherwise be wasted. However, the quality factor of the loop would be low. This brief presents a triple-bias parallel SSHI rectifier, which can effectively enhance the power extraction capability from the piezoelectric (PE) transducer. The circuit has a low complexity and is easy to integrate, which can convert the original one voltage flipping into a triple per half cycle, thereby improving the voltage flipping ratio for low quality factor. The experimental results show that, compared to the traditional SSHI circuit, the power obtained by the load is boosted up to 1.23 X.