This paper reviews recent progress in CMOS RF circuits with respect to technology scaling. It tunes out that RF transceivers almost ideally scale with technologies, even though some of RF circuits do not obey scaling law due to the noise, linearity, matching, and output power constraints. In order to overcome these constraints many design techniques including all digital approach, digital assisted approach, noise cancelling, non-linearity canceling, and RF filtering have been introduced. Also remaining challenges for the future is discussed.

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A new architecture, denoted as the Nyquist folding digital receiver (NYFDR), to compress the data for signal interception is presented. The NYFDR is a digital version of the Nyquist folding receiver (NYFR). Simulation results show that the NYFDR has advantages over NYFR in the detection of Nyquist zone. Moreover, the data rate and resource consumption of the NYFDR are less than those of the digital channelized receiver (DCR).

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Multicast communication has increasingly become common and indispensable for Network-on-Chip (NoC). Router is the key unit of NoC, but few of its implementations provide multicast communication directly. In this letter, we design a tree-based multicast router using differentiated subnetwork. Also, we propose a new deadlock-free routing algorithm to overcome the complex deadlock problem on NoC when it involves multicast communication. In addition, a verification platform on RTL-level is established and synthesized for a Xilinx XC5VLX110T chip. The synthesis reports show that, the multicast router consumes 21.45% less of the chip’s storage resources and 3.82% less of the logic resources when in comparison to the result of unicast router that has the same configuration parameters. The maximum operating frequency is up to 158.203MHz.

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This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5MHz) and 26% power consumption reduction (54.8mW) for 60k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200MHz using the bigram and trigram language models, respectively.

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A Radix-4 Quasi-cyclic shift network (QSN) for reconfigurable QC-LDPC decoders is presented in this paper. A complexity reduction technique is described to reduce the total gate count at each stage in addition to the fact that Radix-4 logarithmic barrel shifter naturally offers less number of stages compared to Radix-2. The proposed Radix-4 QSN architecture supports various code rates and all sizes of sub matrices. Moreover, a novel Radix-4 signal generator is proposed which is particularly an essential element for reconfigurable LDPC decoders. The synthesis, placement and routing (P & R) of the proposed network is performed using TSMC 90-nm standard cell CMOS technology. The implementation results shows that the proposed network outperforms its predecessors by about 11% and 38% in terms of area and clock frequency respectively.

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In this paper, we propose a new composite shielding material using ground granulated blast furnace slag (GGBFS), a by-product of iron refining. To investigate the feasibility of GGBFS inclusion in shielding material, we fabricated a composite GGBFS material and measured its electromagnetic transmission characteristics. First, we measured the permittivity and permeability of GGBFS itself using a 2-port coaxial cable system. After fabrication of the proposed composite GGBFS material, the permittivity of the proposed structure was measured using the resonance cavity method to obtain the basic electromagnetic material properties. When GGBFS is added to an epoxy resin composite material, permittivity increases by approximately 1.5. To show its feasibility as a shielding material, we fabricated planar samples and measured the electromagnetic transmission characteristics between 6 and 12GHz using the free space measurement method. The results show that the sample's shielding level is approximately 1.5dB in the frequency range between 6 and 12GHz for a GGBFS content of 30% and thickness of 2mm. We also obtained a 3dB (50% of incident power) shielding level at 8.5GHz for a 5mm thick sample. The new proposed material in this paper capable for use in many shielding applications and provide a new opportunity for recycling industrial waste.

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This paper presents a programmable and high-efficient application specific instruction-set processor (ASIP) for fast Fourier transformation (FFT) processing based on software defined radio (SDR) methodology. It adopts single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. The proposed ASIP features eight parallel radix-2 butterfly computations with fixed vector data shuffling pattern. In addition, a flexible vector address generation unit is proposed to support inner- and inter-group addressing mode. Experiment results show that the proposed FFT ASIP is much more flexible than previous works and outperforms state-of-the-art FFT ASIP architectures in term of energy-efficiency.

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Sensorless load and position estimation of linear reluctance actuator is investigated in this paper. Due to wide application of these actuators in several industrial automation systems, sensorless techniques are significant to decrease the cost of the system and increase the reliability in the closed-loop control systems. In this paper, based on dynamic model of the actuator and the characteristics of its subsystems, the possibility of sensorless estimation of mechanical parameters is explored. Considering nonlinear behavior of magnetic subsystem, the position of the plunger could be estimated based on the winding inductance and the excitation current value. Then, the amount of load force could be determined based on current value and estimated position. Laboratory measurements of the actuator’s characteristics assist in increasing the accuracy of estimation besides dynamic modeling.

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In this work, a novel digital beamformer applied in vehicle-mounted high frequency (HF) receiving device has been developed. The system adopts robust superdirective beamforming algorithm, which not only effectively reduces the receiving array aperture but also maintains a higher directive gain compared with conventional beamforming method (CBF). The system is designed based on the idea of radio-defined software (SDR), which is easy to update. It contains 16 receiving channels and can output 3 analog beam signals. Experiment shows that the system has fast response and is feasible in engineering.

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In this paper, we proposed an optimized shield design for electromagnetic field (EMF) reduction from the wireless power transfer (WPT) system. Three different cases of shield design are examined in terms of strength of EMF and mutual inductance, which is directly related to power transfer efficiency. Analysis results show that when using both ferrite and conducting sheets as a shield for transmitter and receiver coils, a leakage magnetic field can be significantly reduced with negligible change in mutual inductance. Additionally, the effects of the conducting sheet’s size and thickness on the EMF and the mutual inductance are also examined. Our investigation will be helpful to engineers designing modern WPT systems.

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In this article a novel charge pump circuit is introduced. The proposed circuit utilizes a bulk driven cascode current mirror through an adaptive gate bias technique, that results in a high output impedance over a very wide output voltage range, accurate Charge/Discharge current matching, which minimizes the steady-state phase error in a phase-locked loop (PLL), and low transient glitches. The current variation is less than 0.5µA or 1% over output range. Therefore proposed circuit stabilizes the loop bandwidth of the charge pump PLL and maximizes the dynamic range. The charge pump is designed and simulated under the power supply of 1.8V in 0.18µm CMOS technology to verify the efficiency of the proposed techniques. Monte Carlo process variations and mismatch simulations show that the current variation in the proposed charge pump is very low.

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Photovoltaic (PV) system has been regarded as one of the most popular renewable energy sources due to its easy installation and safe operation. As one of the key control algorithms, maximum power point tracking (MPPT) function of PV inverter has been researched widely. Usually, its performance has been evaluated under a fixed environmental condition including irradiance and temperature. However, recently the dynamic MPPT performance under varying irradiance conditions has been paid attention to the PV society. As the European standard EN 50530, which defines the recommended varying irradiance profiles, was released lately, the corresponding researches have been required to improve the dynamic MPPT performance. This paper presents the design and evaluation of the improved dynamic MPPT performance using the modified P&O MPPT method under EN 50530. By using 250kW PV inverter, the performance of the modified P&O method is evaluated and compared with the conventional P&O MPPT methods. The experimental results show that modified P&O method shows higher dynamic MPPT efficiency under EN 50530than the conventional P&O one.

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We propose a Nyquist optical time division multiplexing transmission scheme using optical root-Nyquist pulses and an optical correlation receiving technique. This scheme can satisfy the Nyquist criterion for zero inter-symbol interference and an optimum detection to maximize the signal-to-noise ratio. Moreover, the processing speed can exceed the speed limitation of electrical devices. We describe the principle and discuss the dispersion tolerance by numerical simulation.

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Squaring and exponentiation of a number are fundamental arithmetic and widely used in the real-time applications such as image processing, digital filtering and cryptography. In this paper, we propose a squaring algorithm of an integer with canonical signed-digit (CSD) number representation. For an n-digit CSD number, our method generates n/4 CSD numbers of 2n-digit length as partial products. This result is half with respect to the conventional squaring algorithms. We implement the squaring circuit based on this algorithm and compare with some existing circuits. Our circuit is 40% faster than the known squaring circuit for binary numbers.

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A 1.0GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42fJ/Conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the area of chip grandly. A new linear and continues offset voltages of dynamic comparator calibration method is presented. This ADC implemented in 65nm CMOS technology achieves SNDR of 48.5dB and SFDR of 58.7dB for 479.5MHz input frequency at the rate of 1.0-GS/s. And the SNDR and SFDR maintain above 48dB and 55dB, respectively, up to 995.1MHz. The power consumption is only 17mW with a supply voltage of 1.2V.

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Retraction notice.

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