This paper proposes an efficient motion vector prediction (MVP) scheme for high speed motion estimation (ME) in H.264/AVC. Though MVP is essential for high coding efficiency, ME with MVP cannot be processed in parallel for high speed implementation due to the dependency of MVP. To eliminate this dependency, the proposed MVP uses the motion vectors in the neighboring macro blocks instead of those in the near sub-macro blocks which are used in the standard. Consequently, high speed ME is possible by using the proposed MVP and the processing time is reduced by up to 88% with insignificant coding quality degradation. The proposed MVP is verified with ME architecture which can encode SD (720×480) resolution video sequence in real-time at 54MHz operation clock with 284K logic gates.

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This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform. It proposes a few useful formulas for the design of a less jitter sensitive NTF. The analytic results and MATLAB simulations show that in the design of an NTF, there is a trade-off between the in-band quantization noise and the jitter induced noise of the modulator.

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We demonstrate high-performance InGaAsP based multiple-quantum-well (MQW) lasers fabricated by low-energy ion implantation induced quantum well intermixing (QWI) technique. Different doses of implantation were used to vary the wavelength shift for MQW lasers from the QWI process. At room temperature, the QWI lasers have continuous-wave (CW) characteristics of 10.4-mA threshold current and 13.8-mW maximal output power, which are comparable to the performance of the lasers made of the same as-grown MQW materials. The QWI lasers have a characteristic temperature as high as 58.4K, which verifies that the material quality after intermixing is feasible for fabricating practical devices.

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An ultra-wide-band CMOS low-noise amplifier (LNA) employing a common-gate (CG) stage for wideband input matching is presented. This LNA utilizes the concurrent noise and distortion canceling techniques. Moreover, the current-reused technique exploiting the passive network instead of using the active and power consuming element is introduced to preserve the power consumption while contributing to the noise canceling trend. In other words, this topology is capable of canceling the noise effect of input transistor without consuming much current. Simulation results based on a 0.13µm standard RFCMOS technology shows that a power gain of 13.5dB and the noise figure of 2.7-4.2dB over the -3-dB bandwidth of 2.6-10.7GHz. With the presence of a weak inversion biased transistor, an input third-order intercept point (IIP3) of +5dBm is achieved. The power consumption is 13.5mW from a single 1.2V power supply.

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DDS (Direct digital synthesizer) is widely used for frequency synthesis. The factors that contribute to spurious signals are analyzed. Adding a random signal to DDS system was used for spurious reduction formerly. Those methods assuredly reduce the spurs while the noise floor of signals is worsened. A new spurious reduction technique based on two DDS is proposed. The first DDS generates the conventional sine signal. The other DDS produces the error signal which compensates for the phase truncation error in traditional DDS system. A spurious reduction circuit has been developed. The experimental result indicates that the spurious signal due to phase truncation can be reduced 8dBc at least.

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