The use of a triple combination of theory, simulation, and lab exercise is most commonly used to promote better student understanding of microwave fundamentals. As part of the RF engineers training education program, an advanced experiments program has been developed in which students can experience successive trial and error procedures including design, circuit fabrication, simulation, and measurement. As a result, it is expected that it be possible for other colleges of technology to use these methods to help students better understand the basis of practical microwave circuit design procedures. In this paper, the design theory and production evaluation process are focused on waveguide inductive and capacitive window.
Motivated by reduction of computational complexity, this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS (MSLMS) algorithm. The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter. The amount of computation of the proposed architecture is not only less than half of the traditional structure, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product (ADP) than the best of existing structures.
GPU spatial multitasking has been proven to be quite effective at executing different applications concurrently using SM partitioning. However, while it maximizes total throughput, latency-critical applications often cannot meet their deadlines due to the increased execution time. Furthermore, SM partitioning cannot allocate the appropriate L1 cache size per kernel. To solve these problems, this paper proposes a new application-aware resource allocation framework called GPU Fine-Tuner, for assigning appropriate resources to GPU kernels. To minimize the execution time of latency-constrained applications, it assigns them more SMs when performance is not affected. It also increases the cache size of SMs for cache-sensitive kernels using resource borrowing from neighbors for cache-insensitive kernels. Experimental results show that the Fine-Tuner outperforms GPU spatial multitasking with up to 15% less average latency without performance degradation.
Additional gating elements are inserted at the outputs of scan flip-flop to freeze unnecessary transitions from scan flip-flops to combinational logic such that the hot temperature is avoided during scan shift. This paper presents a new physical-aware gating element insertion method performed after initial cell placement while satisfying timing and placement density constraints, thus it avoids hotspots during scan shift operation.
The power supply system in mobile application needs to make a tradeoff between large current ability, lower output voltage ripple, fast transient response, good efficiency and component size and so on. The interleaved multi-phase buck topology offers a good solution to this conundrum. In this paper, the relationship between ripple and duty cycle and phase number is established as a ripple cancellation principle. A dual 3-phase buck converter with 2*6 A maximum current ability is designed very suitable for supplying CPUs/GPUs processors. The proposed buck converter is controlled by peak current mode, which contains an automatic phase adjustment module. At last, the design is implemented in a chip fabricated by SMIC 0.18 um process and WLCSP package, with less than 6 mV ripple and above 80% efficiency during load rang up to 4 A.
This paper presents a novel approach to achieve a high Q series negative capacitor (NC). A stepped-impedance distributed amplifier (DA) is used to achieve the negative group delay (NGD) response. The input/output (I/O) impedance of the transistor in each stage is calculated to meet the specific voltage gain coefficient ratio. By this way, the NGD phenomenon can be observed between the input and reversed output ports of DA. A major advantage of this architecture is that the gain is configurable while maintaining a fixed NGD. By properly choosing the gain coefficient, the proposed circuit can exhibit the same S21 as an ideal NC network. From the experimental results, it can be calculated that in 1.4–1.55 GHz the NGD circuit can exhibit the desired equivalent NC value. In addition, thanks to the active structure, the circuit shows a high quality-factor (Q) performance.
Reliability has been an important consideration in designing modern circuits due to the nanometric scaling of CMOS technology. This paper proposes a reliability evaluation approach for logic circuits based on transient faults propagation metrics (TFPMs). In this approach, TFPMs of each nodes are calculated through reverse topological traversal of the target circuit by Boolean operations in parallel. Using these faults propagation features, the reliability of combinational circuits and full scan sequential circuits are evaluated efficiently. Experimental results and statistic analysis show the proposed approach can achieve about three orders of magnitude faster than Monte Carlo simulation (MCS) while maintaining accuracy.
Resistive Random Access Memory (RRAM) is considered as one of the most competitive candidate for next-generation embedded system memories but data security for it has not yet been studied in detail. Since data security of embedded system is becoming more and more important nowadays, we think that it is necessary to study about data encryption for RRAM. In this paper, we studied data encryption candidates for RRAM and conducted several stream ciphers performance experiments for RRAM. As a consequence, we showed that Trivium is the most suitable stream cipher algorithm for RRAM. Also, we analyzed the experimental results.