A 44 GHz frequency band from 252 GHz to 296 GHz has been identified for communications. This frequency band is part of the 300 GHz band, which is expected to be utilized for ultra-high speed wireless communication toward 6G. In this letter, we will discuss the requirements for ultra-wideband wireless communications in the sub-terahertz range, including the 300 GHz band, and clarify the necessity of a communication system based on phased arrays. Finally, a 300 GHz CMOS wireless transceiver capable of transmitting data rates of up to 80 Gb/s that can be utilized as an element of this phased array is presented.
This letter presents a simple approach to design ultra-broadband power amplifiers (PAs). The theories of the hybrid modes class-EFJ PAs are applied. The relationship between the operating frequency and load impedance is analyzed for class-EFJ PAs. By appropriately selecting load impedances at different frequencies, a PA can work well in 1.0-4.0 GHz with high efficiency. In addition, the second harmonic impedance is obtained by combining the selected fundamental impedance and load-pull simulation. For validation, an ultra-broadband high efficiency PA is implemented. Experiments show that output power is from 40.1 dBm to 42.6 dBm and drain efficiency is between 60.6% and 72.7% at the saturation level in 1.0-4.0 GHz. The ACLR is smaller than -27.2 dBc in the same frequency band with an average output power of 35.2 dBm.
Presented is a new type of DC-DC converter and low dropout voltage regulator (LDO) cascaded circuit, which has improved dynamic response and loop stability. In this novel cascaded circuit, the gate voltage of the pass element of the LDO is quantized and compared with a target value to form an error value to finally control the feedback coefficient of the DC-DC converter. Meanwhile, the adjusting speed of this feedback coefficient can be changed dynamically through the gain compensator, which is minimized to obtain the best loop stability when approaching the steady-state and increased to achieve a fast transient response during large dynamic change. The testing results of the prototype designed to verify the feasibility show that the novel cascaded circuit can increase the response speed by 22 times and optimize the voltage ripple by 1.9 times.
System on Chip (SoC) architecture mainly consists of the memories in a larger area. Due to the availability of memories in a larger-size, it is difficult to test these memories for faults. Therefore, a smooth test solution to test these memories against fault and repair the faulty cells has introduced. In this research, we proposed a Memory Test Controller (MTC) to test the memories and Built-in Self-repair (BISR) mechanism to repair the faulty cells for any recent SoC based devices. The MTC not only identifies the fault, but it finds the type of fault available, and BISR block repairs the detected faulty cells. The paper provides empirical insights about how change is brought in features of the SoC based device after integrating both the proposed controller block. It is noticed that from the obtained results, the proposed methods are stands better in terms of the area overhead, power and timing when compared with the existing approaches.
This letter presents a Ka-band receiver front end in the form of system in package using silicon substrate. The front end adopts a dual-channel superheterodyne structure, two GaAs downconverter chips and a power divider chip are integrated on the silicon substrate with an embedded substrate integrated waveguide bandpass filter. Wire-bonding is used for connections and unique impedance matching structure is designed and embedded into the GSG transmission line to compensate for additional insertion loss. The test results show a conversion gain of -13.4 dB without the gain of low noise amplifier. The work in this letter is one of few presentation of a RF system in the form of stacked silicon system in package, revealing the feasibility of stacked silicon in complex RF system implement.
LDPC code has been used widely in NAND flash-based storage system due to its high error correction capacity, prolonging the lifetime of multi-bit NAND flash. However, the LDPC decoding latency degrades the read performance of SSD as it induces more read-retry operations. The last RL (Read-Level) recording method has been proposed in recent research works, which achieves better performance improvement by reducing many useless fail reads. However, these schemes reset the RL of these pages to be 1 after these blocks are erased. Using RL 1 to read these pages may induce many fail reads at first read on each page. That because it ignores the different error source issues, i.e., a part of the page error comes from the P/E cycles, while others come from retention time and other sources. Motivated by this observation, in this paper, we propose two schemes to optimize the read procedure of NAND flash-based SSD, especially for aged SSDs. We propose to record RL induced by different error sources separately, so the RL of the page could keep unchanged rather than 1 after the blocks are erased. The scheme could reduces useless fail read after the blocks are read at first time. We also design a latency aware I/O scheduler to reorder the input read requests in batch by prioritizing requests with low latency to reduce the queue latency. Our experiments show that the proposed scheme can reduce the average response time by up to 33% with less storage overhead.
A novel Si four-wavelength multiplexer (MUX) for CWDM system composed of two types of Mach-Zehnder (MZ) MUX, and a polarization splitter rotator (PSR) based on a tapered asymmetric directional coupler (ADC) and TE1-TM0 mode converter (MC) is proposed and experimentally demonstrated. To make the ADC fabrication-tolerant and broadband, a new design method is proposed, in which waveguide width dependence is taken into account. Although due to the waveguide width change during the fabrication process, the loss of the fabricated ADC is relatively large, a proof-of-concept four wavelength multiplexing is experimentally demonstrated.
A 25Gb/s energy efficient limiting amplifier (LA) with active feedback is presented. To obtain high energy efficiency, the inverter-based amplifier is employed, and the use of interleaving feedback in the four stages enhances the bandwidth of LA core while maintaining a flat frequency response within the -3dB bandwidth. Fabricated in SMIC 55nm CMOS technology, the measurement results demonstrate that the proposed LA achieves a bandwidth of 18.5GHz with a gain of 36.8dB, and consumes only 17.3mW at 1.5V supply voltage, corresponding to an energy efficiency of 0.69pJ/bit at 25Gb/s operation. Due to the absence of passive inductors and capacitors as well as compact structure, the LA core area is only 0.0008mm2.
In this paper, a 30Gbps 1.25pJ/b optical receiver analog front-end (Rx_AFE) mainly consisting of an active voltage-current feedback transimpedance amplifier (AVCF-TIA) and a staggered active feedback limiting amplifier (LA) is presented. By adopting active voltage-current feedback technique in the proposed TIA, the large input capacitance is well-isolated without the limitation of low supply voltage, and the direct contradiction between transimpedance gain and output pole frequency is alleviated significantly. Meanwhile, the bandwidth is further extended by adopting staggered active feedback technique in the LA designing. Fabricated in a 40nm bulk-CMOS technology, the presented Rx_AFE exhibits a transimpedance gain of 63.8dBΩ and a 3-dB bandwidth of 24.3GHz. From supply voltage of 1.0V, power dissipation and power efficiency of the circuit are 37.5mW and 1.25pJ/b respectively, when 30Gbps PRBS is operated. The core circuit occupies a chip area of 920µm×690µm.
The degradation of NMOSFETs due to hot-carrier effects under DC and RF stress was studied experimentally. The experimental results indicate that DC stress leads to more serious performance degradation than RF stress. It has also been found that channel length and width can change the worst DC stress condition. Moreover, RF performance degradation can be explained by DC performance degradation. A new model is proposed to predict the degradation characteristics of devices under RF stress by the degradation under DC stress. By using knowledge-based neural network (KBNN), the model shows good accuracy. It can also reduce test data set and simplify testing process.
Monitoring of training, especially the use of soft devices, is difficult but has become more and more important for human health. In this paper, a self-power flexible piezoelectric sensing system for badminton training based on polyvinylidene fluoride (PVDF) piezoelectric film sensor is designed and experimentally verified. The sensing array is divided as 3×3 chessboard-like areas, which contain thin-film transductors to determine the hitting position and force. The system owns a linear relationship between force and generated electric signal with a sensitivity of 0.377V/N and the minimum sampling interval of 1s. Furthermore, the piezoelectric Lead Zirconium titanite (PZT) patch behind the racket is employed as a power source to support the sensing circle. This work paves a new way for the application of artificial intelligence in the human health area and the Internet of Things.
This letter presents a silicon-based package design for E-band communication systems. As the primary concern to package, the radio-frequency (RF) interconnection from carrier board to the die is carefully designed based on the impedance transformation characteristic of the transmission line (TL). In addition, the simulation results show that the designed interconnection is robust to moderate process deviations. To verify the electrical performance of the designed interconnection, a dummy testing structure is designed, fabricated and measured. The measurement results show that the return loss is less than -10.6 dB in the commercial communication frequency range of 71-86 GHz for E-band applications.