Convolutional neural networks (CNNs) are being widely used in computer vision tasks, and there have been many efforts to implement CNNs in ASIC or FPGA for power-hungry environments. Instead of the previous common representation, the fixed-point representation, this letter proposes a short floating-point representation for CNNs. The short floating-point representation is based on the normal floating-point representation, but has much less width and does not have complex cases like Not-a-Number and infinity cases. The short floating-point representation, contrary to the common belief, can produce a low-complexity computation logic because the operands of the multiplier logic can be shortened by the exponent concept of the floating-point representation. The exponent can also reduce the total length to reduce the SRAM area. The experimental results show that the short floating-point representation with 8-bit total width achieves less-than-1-percentage-point degradation without the aid of retraining in the top-5 accuracy on very deep CNNs of up to 152 layers and gives more than a 60% area reduction in the ASIC implementation.

High-speed optocoupler is widely used in aerospace field, it is required to have tolerance of radiation in the application environment. The key module of optocoupler is optical receiver chip. This paper introduces a kind of radiation-hardened optical receiver chip. A transimpedance amplifier with gain self-regulating circuit, a signal amplitude detector and adjustable inverter, a reference with DTMOS and enclosed gate layout are designed for radiation hardening. The proposed chip is fabricated in a standard 0.5 µm CMOS process. Experimental results indicate that the hardened chip can still work at the total dose of 400 Krad(Si).

An ultra-compact Butterworth low-pass filter (LPF) has been proposed based on through-silicon-via (TSV) technology without investigation the substrate impact. The conductivity of substrate generally leads to noise interference on the passive devices. This letter analyzes the substrate impact on the components, i.e. the inductor and capacitor, and on the whole LPF, by establishing and studying the equivalent circuit model. It is concluded that this type of LPF based on coaxial TSV can be widely used for any-resistivity substrate.

An embossed capacitive micromachined ultrasonic transducer (CMUT) is a device with embossed membrane that works in the collapse mode to improve output pressure in transmission. In this paper, a six-mask sacrificial release process is proposed for fabricating embossed CMUT arrays. Based on this process, the embossed pattern CMUTs were firstly fabricated. By using of electroplating methods, annular embossed patterns made of nickel were grown on the full top electrodes of CMUTs. The dimensions of the embossed pattern were about 3.0 µm in width and 1.4 µm in height. The resonant frequencies of the embossed CMUT array were 6.4 MHz and 8.7 MHz when the device worked in the conventional and the collapse mode, respectively.

This paper presents a 2.4 GHz I&Q passive mixer with 36 dB conversion gain and low biasing current of 1.2 mA. A pre-amplifier sharing biasing current of the trans-conductance stage is used to improve conversion gain and noise performance without dissipating extra power. A gm-boosted common gate structure is proposed as the trans-impedance amplifier (TIA), which consumes less power than an OTA based TIA in traditional passive mixers. A prototype of the proposed mixer is designed and fabricated in SMIC 180 nm CMOS process. The 36 dB conversion gain, −11 dBm IIP3 and 12 dB NF are achieved in measurements.

Hybrid optical-electro Network-on-Chip (HOE_NoC) is a disruptive technology that can provide high bandwidth and low latency for global communication. However, optical links suffers with a problem of large static power consumption in network. For different applications, traffic distribution in space and time may differ largely. Therefore, it is necessary to dynamically provide optical link bandwidth to network for higher power efficiency under all traffic distribution. In this paper, we propose a machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs (RHOE_NoC) to reduce the static power. With machine learning prediction technique, we reconfigure the optical nodes dynamically to adapt different traffic demands while maintaining higher performance. Experimental results shown that as compared to electronic network latency has been reduced by 51%, while throughput has been improved by 14% for 64 node network architecture and energy consumption has been reduced by 26%. We have also compared RHOE_NoC with HOE_NoC without reconfiguration, results show that static energy consumption has been reduced by about 28%.

Optical switches based on silicon (Si) nanowire waveguide exhibit stable performance without active control of operating point owing to its extremely small size. To verify reliability, we carried out simultaneous operation of two Si-nanowire 8 × 8 optical switches in the optical path network that was deployed in Tokyo metropolitan area using dark fibres. System performance was studied transmitting 10-Gb/s WDM signals over two optical paths that were configured in a way that transmitted signals went through the 8 × 8 switches 10 times. Error free performance was achieved over a week without any adjustment of the switches.

Side channel based hardware Trojan detection is one of the most investigated schemes to ensure the trustworthiness of integrated circuits (ICs). However, nearly all of the side-channel methods require a golden chip reference, either a trusted fabricated circuit or layout, which is very difficult to access in reality. In this paper, we propose a golden chip free electromagnetic (EM) side channel simulation and statistical Trojan detection framework. We utilize the design data at early stage of the IC lifecycle to generate EM radiation, and the generated EM traces serve as the golden reference. In order to leverage the EM signatures, a neural network algorithm is utilized for Trojan detection. Experimental results on selected AES benchmarks on FPGA show that the proposed method can effectively detect Trojans with the presence of noise and variations.