In this paper, a novel H-plane T-junction waveguide power divider that can operate on the entire W-band is in troduced, it can save more space in many applications. It solves the problem that the traditional H-plane T-junction waveguide power divider cannot cover the entire W-band and the reflection coefficient is less than -20dB. A H-plane T-junction power divider for the size of WR-10 waveguide are designed and fabricated used a blocking plate, two grooves and a stepped input matching transformer. The measured results agree well with the simulations and It is suitable for the whole frequency band of W, and the reflection coefficient is less than -20dB. The optimized design size can also be used for other waveguides.

This work proposes a quasi-passive reconfigurable complex filter with harmonic rejection based on N-path filtering technique. It features extremely low power consumption and reconfigurable center frequencies. Unlike the traditional N-path filters at RF frequencies, the proposed filter achieves 3rd/5th harmonic rejection at the adjacent frequencies by cascading the N-path filters with different clock frequencies. The filter is implemented in a 55nm CMOS technology, consumes an area of 0.24mm² including all pads. Measured results show that the filter achieves 19dB/34dB harmonic-rejection ratios at 3rd/5th harmonics. At the same time, the overall power consumption is only 0.015mW, and the measured in-band IIP3 is around 7dBm.

This paper proposes a loss minimization control method based on improved gradient descent algorithm (GDA) for interior permanent magnet synchronous machine (IPMSM). Since the power of PMSM is derived from the measured phase voltage and current, this method is independent from the iron loss model containing motor parameters. Meanwhile, it can guarantee the stability of PMSM system when entering the searching period. Both maximum torque per ampere (MTPA) and i_d=0 control are carried out to validate the effectiveness of the proposed method. The experimental results are demonstrated to verify the proposed approach.

To reduce the power consumption of a bio-electrical signal detection system, a level-crossing analog-to-digital converter (LC-ADC) with low power consumption was proposed for biomedical signal detection. An adaptive resolution sampling mode is also designed to reduce power consumption on the original basis. The level-crossing ADC is designed and simulated using a 180-nm CMOS process. The measurement results show that the power consumption is only 197nW, the effective number of bits is 6.4 bits and the signal-to-noise and distortion ratio is 41.6dB under 0.8V power supply voltage. The proposed LC-ADC uses a chip area of 0.147mm² and the FOM is 278fJ/conversion.

This paper presents a multi-octave power amplifier based on a modified simplified real frequency method. The approximate range of the optimal impedance of the transistor in the wide band on the Smith chart is obtained by the load-pull technique, and the coincidence degree of the optimal impedance value and the input impedance value of the matching circuit is taken as a new optimization objective and added into the algorithm. Then the improved algorithm is used to design the amplifier’s wideband matching circuit. In order to verify validity, a 0.5-2.8GHz power amplifier is designed and fabricated. And the measured results show that the saturated output power is between 40.0dBm and 42.8dBm in target band. From 63% to 69% drain efficiency is obtained with a gain from 10dB to 12dB.

This letter proposed a coarse-fine two stages time-based analog-to-digital converter (TBADC). The coarse 4-bit TBADC is pipelined with the fine 5-bit TBADC for high conversion rate. There is one bit redundancy to tolerate the gain and offset mismatch between the coarse and fine stages. The residue is transferred by splitting the capacitor array in a fully passive way, which is non-attenuated and consumes less power. The dynamic VTC in this design has a high linearity over a wide input range. The proposed ADC is designed in a 65-nm CMOS technology. It consumed 3.1mW at 1GHz and had a Walden figure of merit of 15.9fJ/conversion step.

A broadband GaN reconfigurable power amplifier based on band-pass filter matching networks is presented in this work. To realize the reconfigurable power amplifier, closed-form solution theory and distributed PIN switch are used in matching network design. PIN switch controls the branch circuit of the matching network. This reconfigurable PA is designed for 1.2-2.0GHz and 2.2-3.0GHz, which has 10W (40dBm) output power at least and 37.4% drain efficiency (DE) with the power gain higher than 10dB. Measurement results show the designed reconfigurable PA meets the parameters mentioned above, and the correctness of the proposed reconfigurable PA theory is verified.

This paper presents a complementary current-mode 2^nd order Gm-C filter for 5G and other broadband applications. The filter structure is based on 2 complementary differential pairs in order to achieve both low noise and high frequency performances. A bandwidth of higher than 1GHz is achieved with a gain of 0dB and an in-band IIP3 of 29dBm, consuming less than 27mW from a 1.8V supply. The filter is fabricated in a 65nm CMOS process with a core circuit area of 0.1mm × 0.08mm.

This paper presents an improved design and implementation of broadband circularly polarized (CP) antenna that features a broad bandwidth and wide axial ratio (AR) beamwidth. First, the relationship between the three parallel plates (rectangular, semicircular, and semielliptical) and θ is analyzed. The semielliptical parallel plates (PP) used to obtain a wider 3dB AR-beamwidth (104^°×110^°×102^°×118^° at ϕ=0^°, 45^°, 90^°, 135^°, respectively) compared with rectangular and semicircular PP. Secondly, orthogonal crosses with 43^° inclined are used to generate orthogonal fields, and broadband characteristics can be obtained by adjusting the arm of orthogonal crosses. The semielliptical CP-PP antenna prototype was verified by ANSYS HFSS simulation. According to the measurement results, the -10dB return loss is about 20% (24.3-29.7GHz). A gain of 9.22dBic at 27GHz and a 3dB AR-beamwidth of 106^°×105^° at ϕ=0^° and ϕ=90^° are obtained. The designed semielliptical CP-PP antenna can be more beneficial to 5G millimeter wave applications.

High gain, low noise, and low power 920-MHz LNA has been studied. To realize both low noise and low power characteristics, the transistor has to be operated in the moderate inversion region, and to complement gain reduction due to moderate inversion operation, a current-reuse amplifier topology consisting of a vertically stacked cascaded two-stage cascode circuit is designed. The measurement results exhibit S₂₁ of 15.1dB, NF of 2.56dB under a supply voltage of 0.8V, and power consumption of 1.28mW. The process technology used in this study is TSMC 180nm CMOS.