With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and the MOS capacitance variation is the main reason for the change of TSV capacitance and the TCC increases with elevated temperature. Furthermore, the affection of TSV dimensions on TCC are discussed. It is shown that the TCC increases gradually as the TSV radius increases, while the thickness of dielectric layer is the opposite. The cylinder TSV is less thermal sensitive than tapered TSV. This paper provides basis for TSV design considering the temperature effect.
Nanoscale tri-gate SOI MOSFETs attract much attention in terms of the significance of self-heating effects (SHEs) which severely influence the operation stability and device reliability. Here, the impacts of the heat loss paths associated with the SHEs in nanoscale tri-gate SOI MOSFETs are comprehensively analyzed considering the gate dissipation channels (GDCs). The thermal resistance network model and thermal resistance model are presented to illustrate the heat dissipation mechanisms. 3D electro-thermal TCAD simulation results show that the heat flux through the GDCs occupies most part of the total heat dissipation. The static peak temperature can be decreased by decreasing the gate oxide thickness and increasing the cross-section of Fin area of tri-gate devices.
A 60-GHz CMOS receiver front-end with wide IF bandwidth is presented. The receiver front-end consists of an LNA, a down-conversion mixer and an IF buffer. In order to support both channel-bonding and single-channel operations, two types of broadband inter-stage matching networks are analyzed from a new perspective and adopted in the design. Fabricated in a 65-nm CMOS process, the receiver front-end achieves wide IF bandwidth, a 39-dB gain, and a 5-dB noise figure in the high-gain mode. In Channel-2 measurement, the receiver front-end achieves a maximum 3-dB IF bandwidth of 6.83 GHz, which covers three channels and meets the channel-bonding bandwidth requirement.
In this paper, we present a serially-equivalent parallel method to accelerate FPGA placement. Our method is based on Simulated Annealing (SA) Algorithm: moves of placement blocks are processed concurrently on multiple threads. Two strategies are adopted here to guarantee serial equivalency: task switch of the master thread is used to handle data conflicts aroused by parallel; an efficient SA-based parallel framework is designed to obtain orderly flow of data. Our method is tested by doing placement for Xilinx xc4vlx200 FPGA chip. In a quad-core processor, a speedup of 1.8×, 2.7×, 3.4× is achieved on 2, 3, 4 threads. Compared to serial placer, placement results of our parallel placer are deterministic and have no quality loss.
This paper proposed the use of edge plating for direct board-to-board connection. Edge plating offers a contiguous reference plane for array antenna applications and can significantly reduce the loop inductance of power distribution networks.
A novel methodology for designing broadband high-efficiency power amplifiers (PAs) based on the harmonic-tuned is presented in this letter. All harmonics can be effectively manipulated by the innovative structure to achieve high-efficiency and the dual frequencies point harmonic matching method is also applied to the harmonic control network, which has a positive effect on the expansion bandwidth. To verify the validity of the proposed methodology, a gallium nitride PA is designed, implemented, and measured. Measured results manifest a wide bandwidth from 1.1 to 2.5 GHz, with drain efficiency (DE) of 67–86%, saturated output power greater than 39.5 dBm, and large signal gain larger than 9.5 dB. The in-band second and third harmonic suppression levels are maintained at −13 to −36 dBc and −23 to −44 dBc, respectively. Measurement results confirm the theoretical findings reported in this paper.
This brief proposes a differential power analysis (DPA) countermeasure for reconfigurable crypto processors. This method is verified on Field Programmable Gate Array (FPGA). The FPGA runs at clock frequency of 10 MHz, and AES algorithm is mapped on the array. Our countermeasure is based on random delay insertion (RDI), meanwhile keep pipeline processing of data. Effective DPA resistance is achieved by generating delays which subject to approximate uniform distribution and rearranging the processing order of data. This method can improve the difficulty of DPA and keep high throughput. This method also adapt to any other hardware pipeline style cipher processor.