IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 9 , Issue 9
Showing 1-8 articles out of 8 articles from the selected issue
  • Dong-Sun Kim, Sang-Seol Lee
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 822-827
    Published: May 02, 2012
    Released: May 02, 2012
    JOURNALS FREE ACCESS
    Hardware implementation of genetic algorithm processor (GAP) is important for proven effectiveness as optimization engines for real-time solutions. To implement the robust GAP, it is significant to maintain the population diversity for sustaining the convergence capacity and preventing local optimum problem. In this reason, we propose a deterministic mutation method for providing the high population diversity to GAP. Experimental results with mathematical problems and pattern recognition show that the proposed method enhances the convergence capacity up to 34.5% and reduces computation power about 40% compared with the conventional method.
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  • Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park ...
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 828-833
    Published: May 02, 2012
    Released: May 02, 2012
    JOURNALS FREE ACCESS
    In this work, a strategic methodology to determine the channel length limit for the predominance of tunneling mechanism in the operation of a tunneling field-effect transistor (TFET) is suggested and validated for silicon (Si) nanowire TFET device. For quantitative analyses that can be graphitized as a function of channel length, a set of evaluating functions were defined and properly applied. Based on the suggested methodology, the upper limit for keeping the Si TFET under the tunneling-predominant operation turned out to be approximately 65nm in a nanowire structure.
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  • Yoseop Lim, Jaeseok Park, Sungho Kang
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 834-839
    Published: May 07, 2012
    Released: May 07, 2012
    JOURNALS FREE ACCESS
    The demand for fault diagnosis has increased with the increasing complexity of VLSI devices. Recent analysis has found that multiple defects frequently exist in failing chips. Therefore, the diagnosis of multiple defects is very important and is needed in the industry. Here we propose a multiple-defect diagnosis method using an efficient selection algorithm that can handle various defect behaviors. The experimental results for the full-scan version of the ISCAS ’89 benchmark circuits demonstrate the efficiency of the proposed methodology in diagnosing circuits that are affected by a number of different types of defects.
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  • M. H. M. Larijani, M. B. Ghaznavi-Ghoushchi
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 840-848
    Published: May 10, 2012
    Released: May 10, 2012
    JOURNALS FREE ACCESS
    In this letter, a high speed compact structure for 2-bit/step successive approximation (SAR) ADC is presented. Using modified algorithm yields to a simple radix-4 DAC with half bit and a resolution independent Reference Generator unit in the proposed design. This in term caused to extend the resolution of SAR ADC structure for double bit resolutions. An 8-bit SAR ADC is implemented and simulated based on the proposed structure in 300MHz clock frequency and 50MS/s sampling rate. The target design has SNDR=43dB and SFDR=52dB for fin=4MHz at 50Ms/s. The achieved power consumption at this sampling rate is 1.04mW and the Figure of Merits of proposed design will be 175fJ/Conversion-step.
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  • Jae-Ho Nah, Yun-Hye Jung, Woo-Chan Park, Tack-Don Han
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 849-854
    Published: May 14, 2012
    Released: May 14, 2012
    JOURNALS FREE ACCESS
    High-quality rendering via ray tracing requires the tracing of many incoherent secondary rays. In order to accelerate the tracing of incoherent rays, we propose a simple sorting method to increase ray coherence. In this method, we use ray origin buckets and ray direction grids to reorder rays quickly. We implemented our approach on the Manta interactive ray tracer and achieved up to a 1.48× speedup.
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  • Ockgoo Lee, Kyu Hwan An, Juphil Cho, Jaesang Cha
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 855-860
    Published: May 14, 2012
    Released: May 14, 2012
    JOURNALS FREE ACCESS
    A reconfigurable dual-mode monolithic transformer is presented, which avoids the use of switches for load adaptation. The number of turns of primary winding is varied according to power mode control so that load impedance can be optimized for each operation. The concept of the reconfigurable transformer is demonstrated through the design of a multi-mode power amplifier using bulk CMOS process. Electromagnetic and circuit simulation results validate the operation and performance improvements using the proposed transformer. Low power efficiency at 18dBm is substantially improved from 5.5% to 17.5% using multi-mode control.
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  • Liyun Wang, Chun Zhang, Liguang Chen, Jinmei Lai, Jiarong Tong
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 861-867
    Published: May 14, 2012
    Released: May 14, 2012
    JOURNALS FREE ACCESS
    A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiple-bit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100Mev-cm2/mg.
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  • Punithavathi Duraiswamy, Xiao Li, Johan Bauwelinck, Jan Vandewege, Pet ...
    Type: LETTER
    2012 Volume 9 Issue 9 Pages 868-873
    Published: May 15, 2012
    Released: May 15, 2012
    JOURNALS FREE ACCESS
    This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150MHz, we generate RF pulse of 300MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.
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