A novel quarter mode substrate integrated waveguide (QMSIW) resonator is proposed, based on which a plane cascade QMSIW tunable filter is designed. Miniaturization of the filter is achieved, whose area is only 0.51λg × 0.34λg. The filter works at 1.2 GHz with the tunable range of 31.6% and the fabricated insertion loss less than 1.9 dB and return loss greater than 15 dB, respectively.
A 60 GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage’s transistor of power amplifier (PA) and the first stage’s transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 dB minimum noise figure (NF) in the receiver mode is measured, and 2 dBm of OP1dB is measured in the transmitter mode.
Compressive sensing (CS) is perceived as a breakthrough in sampling theory, as it proves that sparse signals can be reconstructed from fewer samples than required by the Shannon-Nyquist theorem. However, CS can hardly be applied to real-time applications because reconstruction algorithms are computationally demanding. To tackle this problem, in this paper, we propose a new high-speed architecture for implementing the orthogonal matching pursuit (OMP), which is one of the most popular algorithms for CS reconstruction. Specifically, a novel pipelined systolic architecture and an optimized scheduling strategy are proposed. From the synthesis results, we find that the proposed design takes 1.638 µs to reconstruct 16-sparse signal, which is 19.2 times faster than the existing VLSI implementation of the OMP.
Power analysis attacks are major concerns among all kinds of side channel attacks. This paper proposes three kinds of countermeasures for Differential Power Analysis (DPA) attacks by fully exploiting characteristics of a many-core processor: (1) Data-level parallelism, (2) Random Dynamic Task Scheduling (RDTS), and (3) Random Dynamic Adjustment (RDA), which combines RDTS, Random Dynamic Frequency Scaling (RDFS) and Random Dynamic Phase Adjustment (RDPA). For the first time these techniques are applied to a multicore processor from the perspective of secure system design. AES algorithm with mentioned countermeasures is implemented on an 8-core processor. Simulation results show that these countermeasures considerably improve the system security with little performance overhead.
The full-bridge topology is generally used in the post stage of inverter, to realize dc-ac voltage conversion. Inherent shortcomings of full-bridge such as high-side switch driving, prone to shoot-through and substantial power loss are inevitable. A topological solution is proposed in this letter, by means of improving the original coupled-inductor Watkins-Johnson topology into dual low-side switch version and conducting synchronous control. Theoretical analysis and experimental results indicate that the improved topology is capable of generating pure sinusoidal ac output. The merits include ease of driving, low power loss, nonpulsating terminal currents, immunity to shoot-through, simple control strategy and so forth.
This letter presents an energy-efficient VLSI architecture for SVM classification. Instead of accurate calculation, cost-reduced computing elements based on approximative techniques are designed to complete computation-intensive operations in the SVM-based classifier to save energy and resources. Besides, a partial parallel structure is applied to eliminate dimensional constraints for inputs of classifiers and balance between classification speed and energy consumption. We adopt 55-nm CMOS process to implement the proposed design. It occupies 0.0901 mm2 area and consumes 15.9 mW at operating frequency of 100 MHz and from an operating voltage of 1 V. Experiment shows that the design provides an area reduction by 41.5% and a significant saving in energy efficiency by 61.8% compared with the baseline model.
In this paper, a compact dual-beam shorted-patch antenna is presented for wireless communications at 5.8 GHz. A short-end coplanar waveguide (CPW) feed line integrated on the ground plane is adopted in the structure to provide dual beam characteristic. The metal via array is applied in order to adjust the resonant frequency. The simulated results dual-beam radiation in the E-plane has maxima at +45° and 135°. The measured radiation pattern is dual-beam and the peak gain is 6.11 dBi at 5.8 GHz.
Motivated by reduction of computational complexity and improvement of convergence speed, this work develops a high-speed VLSI realization of the adaptive FIR filter based on the delayed dual sign LMS (DDSLMS) algorithm. Not only is the computation of the proposed algorithm the same as that of the sign LMS algorithm, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 38% less power and nearly 43% less area-delay-product (ADP) than the best existing structure.
This paper presents a low phase noise multi-band LC VCO using a switched differential inductor in a standard 0.18 µm CMOS technology. In the proposed LC VCO, it is achieved multi-bands of 0.9, 1.8, 2.4, and 4.5 GHz, and the phase noises of −133, −135, −125, and −127 dBc/Hz at 1 MHz offset, respectively. The chip size is 1.0 × 1.1 mm2 including pads. The DC power consumption is 16.2 mW at 1.8 V supply voltage.
A new low-power, fast-lock duty-cycle corrector (DCC) circuit with a digital duty-cycle adjuster (DCA) for mobile LPDDR3/LPDDR4 DRAMs is presented. The proposed DCC utilizes a digital feedback delay element (DFDE) to achieve wide duty-cycle correction and operating frequency ranges with low power consumption and fast lock capability. To obtain fast locking time and high duty-cycle correction accuracy, a 6-bit successive approximation register (SAR) controller utilizing a hybrid search algorithm is adopted. The measured duty-cycle error is less than ±0.85% over a 30–70% input duty-cycle range at 0.2–1.5 GHz. The DCC, which is fabricated in a 0.13-µm CMOS process, dissipates only 1.9 mW at 1 GHz and occupies an area of 0.036 mm2.
To study the strain and temperature distribution during the carbon fiber wound composite curing process, the fiber Bragg grating (FBG) sensors were used to monitor the temperature and strain distribution of the carbon fiber composite ring specimen during the curing process. The results show that the FBG sensors can effectively monitor the strain and temperature distribution inside the ring specimen during the curing process. The trends of temperature changes at different thickness are similar. However, there is an obvious temperature gradient and the temperature difference between the surface layer and the inner layer is up to 6.2°C. In the stage of heating and heat preservation, the inner strain of the ring specimen near the mould during the curing process is positive, and the strain change outside the specimen is always negative. During the natural cooling stage, the internal strains of the specimen changed greatly. After the curing, the inner and outer layers show the shrinkage strain of different values. This indicates that there is an uneven cure residual stress in the cured ring specimen.