IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 17 , Issue 14
Showing 1-4 articles out of 4 articles from the selected issue
LETTER
  • Punithavathi Duraiswamy, Satishkumar, Raghu, Shankar K. Selvaraja
    Type: LETTER
    Subject area: Circuits and modules for electronic instrumentation
    2020 Volume 17 Issue 14 Pages 20200197
    Published: July 25, 2020
    Released: July 25, 2020
    [Advance publication] Released: June 25, 2020
    JOURNALS FREE ACCESS

    90° phase shifters are used in various communication applications such as analytic signal (I and Q) generation, image rejection and Single Side Band (SSB) modulation. In this article, we present an efficient VLSI architecture for the generation of IQ signal with reduced amplitude and phase mismatches using phase-orthogonal FIR phase shifter. The proposed design and implementation reduces the constant multipliers in FIR filter from 2N to N/2 in two steps. In the first step, the filter passband is centered around 0.25fs which makes the alternate filter coefficients zero, reducing the multiplier count to N. In the second step, the hardware architecture is designed in such a way that the time-reversal property of the two filters is exploited to reduce further the multiplier count to N/2. A transposed FIR filter structure with Canonic Signed Digit(CSD) coefficients is adopted for implementation on FPGA. The dual filter approach and the optimization technique has resulted in better filter performance compared to the conventional Hilbert filter approach. The FPGA implementation gives a phase and amplitude ratio error of -0.17° and 0.0002 dB for a filter order of 26 and -0.21° and 0.0053 dB for a filter order of 32 respectively. Despite having two filters, the area increase is only 50% of widely used Hilbert transformer method that uses a single FIR filter. The designed phase shifter shifter is used to simulate an SSB modulator. A side band suppression of 18.9dB is achieved with the proposed phase-orthogonal phase shifter, which is ≈8 dB better than the Hilbert filter based SSB modulator.

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  • Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyu ...
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 14 Pages 20200198
    Published: July 25, 2020
    Released: July 25, 2020
    [Advance publication] Released: June 30, 2020
    JOURNALS FREE ACCESS

    In this letter, we propose a method to precisely extract on-chip capacitance in a transistor level with the minimal signoff data. As electromagnetic compatibility (EMC) concern in this work, a precise estimation of on-chip capacitance is important for designing a power delivery network (PDN) of LSI-package-board systems. However, the conventional methods require additional libraries other than the signoff data to extract the capacitance in a chip level. The proposed method improves accuracy of the extracted capacitance by simulating the device intrinsic capacitance simultaneously in the transistor level and enabling us to utilize commonly used design resources and flow as well. The experimental results show that the capacitance of a fabricated chip in 130 nm technology estimated by the proposed method is within 8% error compared to the measurement of the capacitance. The whole extraction process can be done within a short period of time.

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  • Qian CHEN, Jianwei HAN, Yingqi MA, Sai LI, Jingtian LIU, Yaqing CHI, B ...
    Type: LETTER
    Subject area: Electron devices, circuits and modules
    2020 Volume 17 Issue 14 Pages 20200205
    Published: July 25, 2020
    Released: July 25, 2020
    [Advance publication] Released: July 09, 2020
    JOURNALS FREE ACCESS

    A short-time high-dose gamma ray will produce many electron-hole pairs by the Compton effects in various semiconductor materials. Then pulse current will be generated in the devices and electronic system and affect their normal operation, which is called the Dose Rate Effects (DREs). Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the impacts of well structures on the DREs in 65-nm bulk CMOS inverter which is the most basic circuit unit are investigated. In this paper, the extend Gamma Radiation Model is used in simulations for effectively simulating the generation of electron-hole pairs in circuits. And present a idea for radiation hardening of bulk silicon CMOS circuits approach to DREs through optimization of well structure. The results of the simulations show that deep P-well (DPW) structure effectively reduces pulse amplitude of the voltage while the deep N-well (DNW) structure reduces the pulse amplitude only in high doping concentration. In addition, the pulse amplitude decreases with the doping concentration of deep well increasing. The mechanism is analyzed from the aspects of charge collection and potential change.

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  • Wenxiang Zhen, Shaojun Li, Shurui Cao, Yongbo Su, Zhi Jin
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and modules
    2020 Volume 17 Issue 14 Pages 20200215
    Published: July 25, 2020
    Released: July 25, 2020
    [Advance publication] Released: July 14, 2020
    JOURNALS FREE ACCESS

    This letter presents a broadband 2:1 static ECL frequency divider in a 0.8 μm InP DHBT process. The proposed divider is based on an ECL double emitter-followers structure. The maximum cut-off frequency (ft) utilization of the device is improved up to 0.967 through theoretical analysis and calculation. The measurement shows that the divider can operate with input frequency from 1 GHz to 62 GHz in sinusoidal waveform, while the maximum ft of the device is 150 GHz. Bandwidth utilization BW/ft is 0.413, which is an extremely high value for InP devices at the same size.

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