IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 8 , Issue 15
Showing 1-9 articles out of 9 articles from the selected issue
LETTER
  • Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh ...
    2011 Volume 8 Issue 15 Pages 1204-1209
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.
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  • Takuji Kousaka, Hiroyuki Asahara
    2011 Volume 8 Issue 15 Pages 1210-1214
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    This paper addresses the first experimental demonstration for the nonlinear dynamics in a simple PWM-1 controlled interrupted electric circuit with one dimensional discrete map. First, we show the circuit model and explain its dynamics. Then, the discrete map is mathematically defined for the rigorous analysis. Finally, we show the laboratory experiment and discuss about the circuit's fundamental characteristics.
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  • Tsuyoshi Funaki, Yuki Nakano, Takashi Nakamura
    2011 Volume 8 Issue 15 Pages 1215-1220
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    SiC power devices with low loss and fast switching capability have been developing. This study experimentally characterizes trench gate and planar gate SiC MOSFETs, and discusses the difference to conventional Si MOSFET in terms of static and dynamic performance. First, the static current-voltage (I-V) characteristics are evaluated to assess conduction loss. Next, the bias voltage dependencies of terminal capacitance (C-V) are characterized to clarify differences stemming from device configuration. Turn-off switchings for non-inductive resistive loads are examined, and the result are evaluated by associating measured C-V characteristics.
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  • Keizo Inagaki, Takashi Ohira, Tetsuya Kawanishi, Masayuki Izutsu
    2011 Volume 8 Issue 15 Pages 1221-1227
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    We developed a beam forming network (BFN) for an array antenna with 5 elements radiating 3 independently steerable beams, and measured the phase shift characteristics. The main part of the BFN is integrated as a single photonic integrated circuit (PIC) chip using birefringent Lithium Niobate (LN) waveguide. The phase distribution among the 5 element antennas is controlled by the wavelength tuning of an optical RF source. Highly linear phase shift characteristics with the sensitivity of 8.24°/nm are achieved. By using 3 tunable optical RF sources allocated to different wavelength range, the PIC chip can generate feeding signals for 3 independently steerable beams.
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  • Moein Nazari, Ahmad Mortezaie, Ayaz Ghorbani, Gholamreza Moradi
    2011 Volume 8 Issue 15 Pages 1228-1233
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    A wideband design model for 4×4 microstrip Rotman lens is presented, with a precise behavior of return loss of the ports and their phase centers. The procedure for choosing the optimum geometrical parameters of lens and modifying the curvature of sidewalls yield a very wideband lens. Based on the presented model, a prototype has been built for the true time delay phasing of an antenna array for the frequency range from 8GHz to 26GHz. The fabricated 4×4 Rotman lens has an average amplitude error of 0.5dB and phase errors of 2 degree. All the beams have a fixed position in frequency band and the maximum deviation of the beams from the ideal position is less than 0.65 degree.
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  • Mochan Yang, Yoan Shin
    2011 Volume 8 Issue 15 Pages 1234-1239
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    We propose an ATI (Adaptive Tone Injection) scheme based on clipping noises for PAPR (Peak-to-Average Power Ratio) reduction of OFDM (Orthogonal Frequency Division Multiplexing) signals. The proposed scheme is composed of three steps: clipping, tone selection, and TI procedures. In the first step, the peak samples in the inverse fast Fourier transform outputs are scaled down by the clipping. In the second step, two tone positions where the powers of the real and imaginary parts of the clipping noises are the maximum, are selected. Finally, the generic TI procedure is performed for the selected tones. Simulation results show that the proposed scheme significantly reduces the complexity of the original TI, while maintaining the PAPR reduction performance.
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  • Yang-Han Lee, Yih-Guang Jan, Hsin Huang, Qiang Chen, Qiaowei Yuan, Kun ...
    2011 Volume 8 Issue 15 Pages 1240-1244
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    The received power imbalance (RPI) effect exists in multiple antennas wireless communications system due to design flaw, operator's negligence etc. The range of RPI can be from -10dB to 0dB and if the RPI information is not available at the receiver terminal, it can implement turbo iterative receiver by concatenating multi-input and multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) demodulation (MIMO OFDM demodulation, MOD) serially by channel decoder such as low density parity check (LDPC) decoder or Convolution code (CC) decoder to mitigate the RPI effect and to maintain the system performance at certain acceptable level.
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  • Ching-Che Chung, Duo Sheng, Sung-En Shen
    2011 Volume 8 Issue 15 Pages 1245-1251
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65nm CMOS process, and the power consumption is 1.52mW at 250MHz and 5.83mW at 1GHz, respectively.
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  • Yen-Chia Chu, Le-Ren Chang-Chien, Dariusz Czarkowski
    2011 Volume 8 Issue 15 Pages 1252-1259
    Published: 2011
    Released: August 10, 2011
    JOURNALS FREE ACCESS
    Low-drop-out (LDO) voltage regulators have been widely used in the power supply of the integrated circuits (ICs). With the evolution of the IC manufacturing process and its applications, the design of the analog controlled LDO has encountered more challenges in recent years. This paper starts with the discussion of low supply voltage and low output capacitor problems that have been found in the analog controlled LDO. To solve the mentioned problems, a novel design concept of the digitally controlled LDO is then presented. To verify the feasibility of the real implementation, the designed circuit is validated using the NanoSim/VCS software in a 0.18µm manufacturing process before the circuit is taped-out. With the test condition of 1V supply voltage, the stability of the proposed LDO is guaranteed when a small output capacitor (1µF) with very low equivalent series resistance(1mΩ) is used. Load test result shows that the output voltage spike is only 40mV with 3µs recovery time when the load current steps-up from 1 to 51mA.
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