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Mohammad Tohidi, Alireza Abolhasani, Khayrollah Hadidi, Abdollah Khoei
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130364
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 23, 2013
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This paper presents a new high speed 5-2 compressor. It is designed based on a new truth table which leads to a simple structure. Also, the driving problems are reduced. Due to the similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays and the power dissipation is decreased. Furthermore, by use of full swing logics, the speed of cascaded operations is enhanced. The latency of proposed design is 440ps.
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Zhiyong Zhao, Xiangyang Li, Wenge Chang
Article type: LETTER
Subject area: Electron devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130514
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: August 28, 2013
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Coherence is an important quality of radar signal. DDS + PLL Hybrid scheme becomes one of the most important and dynamic research in signal generating. In this paper, a novel DDS + PLL Hybrid scheme with the sweeping voltage circuitry is proposed to solve the problems in the classical scheme, such as poor stability, large design difficulty and long acquisition time. Meanwhile, pre-distortion is also proposed to compensate the static phase error, which improves the coherence and pulse compression performance. The measurements of the test system indicate the proposed scheme reduces the acquisition time and improves the coherence effectively.
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In-Gul Jang, Kyung-Ju Cho, Hwan-Yong Kim, Jin-Gyun Chung
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130530
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: August 15, 2013
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In this paper, we propose a new memory efficient IFFT design method for OFDM-based applications, based on a signed integer mapping of three IFFT input signals which are composed of modulated data, pilot and null signals. The proposed method focuses on reducing the word size of memory in the first two stages of the single-path delay feedback (SDF) IFFT architectures since the first two stages require 75% of the overall memory. By Synopsys simulation of the first two stages of IFFT, it is shown that the proposed method achieves about 40% reduction in area and 44% reduction in power consumption compared with the previous work.
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Ehsan Kargaran, Negar Zoka, Abbas Z. Kouzani, Khalil Mafinezhad, Hooma ...
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130557
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 22, 2013
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A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18
μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP
3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S
21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.
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Hai Liu, Motoyuki Sato
Article type: LETTER
Subject area: Microwave and millimeter wave devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130573
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 23, 2013
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We propose a new method for the antenna phase center determination based on measurement. The phase center position and the delay of wave propagation through a Vivaldi antenna are estimated from the measured arrival-time of a multi-offset transmission signal. The estimated phase center position agrees well with that determined by a numerical simulation. The estimated delay has also been validated to have a good accuracy by a laboratory experiment. Then we demonstrate that the accuracy of the range distance estimation by a radar system using a Vivaldi antenna can greatly be improved by considering the phase center position.
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Lei Li, Guodong Li, Yingxu Zhao, Pengsheng Yin, Wanting Zhou
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130628
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 17, 2013
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{2
n, 2
n-1, 2
n+1} is one of the most commonly used moduli in residue number systems. In this express, we propose a novel comparator for the moduli {2
n, 2
n-1, 2
n+1}. Based on the proposed architecture, we can design high speed comparator for the moduli {2
n, 2
n-1, 2
n+1}, which is the fastest among all known comparators for the moduli {2
n, 2
n-1, 2
n+1}. The performance of the proposed comparator is evaluated and compared with the earlier fast comparators for the moduli {2
n, 2
n-1, 2
n+1}, based on a simple gate-count and gate-delay model. The proposed comparator can improve the state-of-art by 8% on the average in terms of area and 6% on the average in terms of performance delay.
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Zhichao Zhang, Anh Dinh, Li Chen, Muhammad Khan
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130672
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 10, 2013
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In this paper, an input inductive network for the wideband LNA is proposed. The two input inductors located in and out of the feedback loop are set respectively to combine with the conventional resistive feedback structure. Input matching and NF of the LNA can be optimized separately by varying the value of the two input inductors without significant influence from one to the other. The proposed cascode LNA was analyzed, designed, and fabricated in the IBM 0.13
μm CMOS technology to verify the concept. A −10dB S11 is achieved in a wide range of frequency from 1GHz to 3GHz. Within this bandwidth, the LNA has a gain of 7.5dB and a minimum noise figure of 2.5dB while consumes a 7mW of power. The results indicate that the proposed input-network effectively alleviates the tradeoff between noise figure and bandwidth without requiring extra power consumption.
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Hiroya Tanaka, Junya Muramatsu, Toshiaki Watanabe, Yoshiyuki Hattori
Article type: LETTER
Subject area: Microwave and millimeter wave devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130679
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 11, 2013
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A compact path-loss measurement system for design of in-vehicle short range communication is proposed. The system is composed of sensor network modules for data transmission and a transceiver for the sounding signal. The channel is measured in an engine compartment of a hybrid vehicle using the developed system. As a result, it is clarified that the engine compartment has a severe fading channel.
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Na Zhang, Huaxi Gu, Yintang Yang, Zheng Chen, Ke Chen
Article type: LETTER
Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
2013 Volume 10 Issue 21 Pages
20130681
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 22, 2013
JOURNAL
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In optical Network-on-Chip (NoC), packet switching remains popular owing to its scalability and reliability. Considering no mature optical buffering technology, deflection routing is preferable to resolve the output port contention. Reduction of deflection probability is essential to bufferless deflection optical NoC. This letter proposes a new 5*5 router architecture, and especially a deflection-supported switching fabric. Moreover, an ejection unit and an injection unit are designed to reduce the deflection. Additionally, priority-based routing computation and port allocation algorithms are designed based on the new switching fabric. The simulation results show that our proposal can improve performance at acceptable insertion loss.
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Zhuohui He, Wu Ye, Suili Feng
Article type: LETTER
Subject area: Microwave and millimeter wave devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130687
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 29, 2013
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The memory polynomial (MP) model is a frequently used structure for digital predistortion (DPD) of power amplifiers (PAs) in wireless communication systems, but it has limited performance. In this paper, we propose a compound memory polynomial (CMP) model to enhance the accuracy. The CMP model is constructed by adding the terms concerning the difference of the input to the MP model. The effectiveness of the CMP model is demonstrated experimentally.
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Qingchen Zhou, Huotao Gao, Huajun Zhang, Lin Zhou, Fan Wang
Article type: LETTER
Subject area: Electromagnetic theory
2013 Volume 10 Issue 21 Pages
20130715
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 16, 2013
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Low side lobe level (
SLL) and forming nulls can help to realize high-frequency (HF) superdirective receive arrays. In this letter, we reformulate the problem of designing an HF superdirective receive array as a problem of pattern synthesis. Based on the adaptive array theory, we present a numerical pattern synthesis algorithm combined with the design of HF superdirective receive array. Compared with the existing methods for superdirective array design, new method has more advantages in suppressing interferences and clutter. To confirm the effectiveness of novel method, numerical simulations are conducted.
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Bin Zhang, Yan Han, Shifeng Zhang, Dazhong Zhu, Wei Zhang, Huanting Wu ...
Article type: LETTER
Subject area: Electron devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130719
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 17, 2013
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A novel high-voltage trench gate insulated gate bipolar transistor with diffusion remnant (DR) layer (DR-IGBT) is proposed in this letter. The DR layer in the emitter side which is formed by grinding after ultra-deep N
+ diffusion helps to stored the carrier and improves the on-state voltage drop (V
ce(SAT)). The DR-IGBT has a better trade-off between the breakdown voltage (BV) and V
ce(SAT) than the carrier stored trench bipolar transistor (CSTBT). The doping profile of diffusion remnant layer makes the junction of the p-base/DR layer nearly linearly graded junction, which does not decline the BV too much. The depth of the diffusion remnant layer and N
+ diffusion layer less impacts BV and V
ce(SAT) unless the diffusion depth is reduced.
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Atsushi Watase, Hirokazu Kubota, Yuji Miyoshi, Masaharu Ohashi
Article type: LETTER
Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
2013 Volume 10 Issue 21 Pages
20130740
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 18, 2013
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We propose a simple method for measuring the mode power of two-mode fiber based on the bending method. The mode power ratio is determined with better than 1dB accuracy by undertaking three power measurements with different numbers of fiber bends. We also evaluate the estimation error of the proposed method and the required resolution of the measurement.
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Tsuyoshi Funaki
Article type: LETTER
Subject area: Electron devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130744
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 16, 2013
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High
dv/dt caused by the fast switching of high voltage induces misfiring of adjacent power MOSFETs by a fluctuating gate voltage. This is known as the self turn-on phenomenon. The gate voltage of vulnerable power MOSFETs is increased by charging the Miller capacitance with the abrupt application of a drain voltage, even though the gate drive circuit maintains the off condition. This study analytically derives the model equation of gate voltage behavior and experimentally compares the difference in the phenomena between high-voltage Si super-junction MOSFETs and SiC MOSFETs on the basis of static C-V and dynamic characteristics. The results show that the gate voltage of SiC MOSFETs is insusceptible to a high-voltage fast switching operation.
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Ki-Chai Kim, Wonzoo Park, Kwang-Sik Lee
Article type: LETTER
Subject area: Electromagnetic theory
2013 Volume 10 Issue 21 Pages
20130750
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 17, 2013
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This paper presents the electric shielding effectiveness (SE) of a dual metallic wall with narrow slots when the plane wave is incident. In the analysis, integral equations for aperture electric fields on slots are derived and solved by applying Galerkin’s method of moments (MoM). The numerical results show that plane-wave SE depends on both slot lengths and plate spacing for a given frequency. Plane wave SE fluctuates with the spacing of the plate, and the fluctuation period is about 0.5λ. A high level of electric SE can be obtained for small slots and low frequencies. Also obtained is the electric SE below 0dB when the plate spacings are smaller than 0.1λ. Experimental measurements are also presented to validate the theory.
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Ic-Pyo Hong
Article type: LETTER
Subject area: Electromagnetic theory
2013 Volume 10 Issue 21 Pages
20130762
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 23, 2013
JOURNAL
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In this letter, we calculated the propagation path loss because of the vertical electric dipole on perfect electric conductor ground in time domain. We derived the electric field in time domain and calculated the transient response and the received signal strength. The results show that the changes in the height of the base station caused the changes in the transient response in time domain and that such changes also affect the changes in received signal strength and the location of the near field because of the effects of ground surface. It is expected that such results can be applied in mobile communication network design and in military communication such as ground surface radars.
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KeeChan Park, SangYun Kim, JaeHyeong Jang, SooHo Cho, SeungO Kim, JaeW ...
Article type: LETTER
Subject area: Electron devices, circuits, and systems
2013 Volume 10 Issue 21 Pages
20130765
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 18, 2013
JOURNAL
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The shift register comprised of metal-oxide thin-film transistors (TFTs) is apt to exhibit anomalously high power consumption because the oxide TFT often has depletion-mode characteristic. We have developed a new shift register circuit in which one of the pull-down TFTs is controlled by capacitive coupling with the clock signal and the input carry signal. Employing this structure, the TFTs with non-zero V
DS are always turned off with negative V
GS. As a result, unnecessary current through the TFTs is eliminated and the power consumption of the new circuit decreases to the half of our previous one when the threshold voltage of the TFT is −5V.
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Hui Yang, Shuming Chen, Jianghua Wan, Huanyao Dai
Article type: LETTER
Subject area: Integrated circuits
2013 Volume 10 Issue 21 Pages
20130798
Published: November 10, 2013
Released on J-STAGE: November 10, 2013
Advance online publication: October 29, 2013
JOURNAL
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Wide Single Instruction Multiple Data (SIMD) architectures are very important in the compute-intensive applications, but less efficient for applications with cross-iteration dependency loops which are difficult to parallelize and vectorize. This paper introduces Decoupled Iteration Mapping (DIM), a technique that dynamically maps a cross-iteration dependency loop onto the improved SIMD architecture which achieved multicore-like thread-parallel performance. The minor modification on the baseline architecture is composed of a Prefetch Unit & Instruction Buffer Array (PU&IBA), a Loop Control Unit & Instruction Dispatch Unit (LCU&IDU), and a Data Buffer Chain (DBC). Experimental results show that, the proposed DIM scheme can achieve average 3.04x performance speedup with a cost of only 6.44% area overhead.
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