Utilizing the randomness caused by process variations in chip manufacturing, PUF can provide identification and verification by generating unique challenge-response pair. The output response of Arbiter PUF is due to path delay differences from different input challenge. However, due to the strong linear correlation between the response and challenge of the Arbiter PUF, the attacker can model the APUF through a machine learning algorithm. This paper proposes a challenge pre-processing structure arbiter PUF (CPP-APUF), which increases the unknowingness of the input challenge, and improves the APUF’s ability to resist machine learning attacks. The 64-stage CPP-APUF is implemented based on FPGA, the machine learning algorithm is used to attack the CPP-APUF. The output response prediction accuracy is lower than 61.33%, which is effective against the modeling attack of machine learning. Finally, the challenge-response pair obtained from experimentally verifies the PUF characteristics.
In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer, which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance (Ron,sp) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the Ron,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the Ron,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.
An antenna array system with high angular resolution is proposed to adapt the demands of both medium-range radar (MRR) and long-range radar (LRR) detections for 77 GHz automotive radars. Both the MRR and LRR modes are integrated into one substrate based on the optimized sparse array topology, which makes full use of the antenna aperture size to improve the angular resolution of the proposed system. Two-dimensional series-fed weighting arrays are designed via the Taylor synthesis method to effectively heighten the antenna gain and restrain the sidelobe level. After completing the fabrication, measurement results of the proposed antenna array are in good agreement with the simulation results. Moreover, the angular resolution is verified to be 0.5° by adopting the coherent signal space method (CSM) with stepped frequency transmitting waveform, which validates the effectiveness of the proposal.
We propose and demonstrate the lateral integration of a VCSEL and a slow-light VCSEL amplifier with in-plane resonant wavelength detuning design, enabling the unidirectional coupling and stable single-mode operation with good beam quality. The modelling and simulation result of the wavelength detuning and unidirectional coupling is shown. A slow light laterally coupled from the VCSEL to the amplifier can be amplified uniformly when the amplifier is pumped above the threshold current. We also present the experimental data of the beam quality, output power and spectrum. The measured data show the increased single-mode output power with good beam quality in comparison with conventional VCSELs. A record single-mode power (40 mW) with narrow beam divergence (<0.06°) is presented.
A hysteresis controlled MPPT method is proposed to improve the efficiency of piezoelectric energy harvesting (PEH). According to the characteristics of the PZH output power, the maximum output power can be obtained when the piezoelectric transducer (PZT) output voltage is controlled nearby the 1/2 open-circuit voltage (optimal output voltage). A hysteresis window for maximum power point controlled is implementing with the energy storage circuits, which optimize the voltage of PZT output after rectification to optimal output voltage. Experimental results show that the MPPT control method with the hysteresis window can effectively track the optimal output voltage. The maximum power tracking efficiency ηMPPT is high to 98.7% with the variety of the ambient vibration energy.