To design a high-precision and low-complexity FFT/IFFT processor architecture, the optimum bit sizing technique in each stage is usually adopted. However, it is difficult to provide an accurate, fast word length scheme due to the diversity of FFT algorithms and the complexity of circuit structure. In this paper, we focus on the widely-used radix-2k Decimation-In-Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Based on our previous research on fixed-point FFT Signal-to-Quantization-Noise Ratio (SQNR) assessment, an analytical expression of word lengths in different stages is deduced. We further put forward a word length optimization method based on the analytical expression. Pre-layout logic synthesis and power simulation are performed for comparison with some previous works. Eventually, we implement a 16384-point FFT processor in 0.13 µm technology. The proposed method yields more hardware resource benefit and saves more simulation time.
This study demonstrates the design and theoretical analysis of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages. Theoretical analysis for evaluating the limit of jitter reduction is also presented.
Buck converter is widely used in the aerospace field. However, radiation in the aerospace environment will result in degradation or failure of devices and circuits. This paper presents a radiation-hard Buck, which is an adaptive on-time Buck. A radiation-hard adaptive on-time generator is proposed by utilizing of leakage current compensation. The proposed radiation-hard adaptive on-time generator is composed of an adaptive on-time timing block and a charging current generator. Finally, the proposed Buck is fabricated in a standard 0.18 µm BCD process. And the radiation tests show that the Buck still maintains stability after total ionizing dose irradiation at a total dose of 350 Krad (Si).
This paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed dynamic random-access memory (DRAM) channels, with an aim to facilitate an automated test procedure for a DRAM interface, which does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that has experienced adjustable amounts of skin-effect loss and dielectric loss in electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and low-bandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip, fabricated in a 65-nm CMOS process, occupies an area of 5200 µm2 and operates over 1.4–7 Gbps while dissipating 38 mW at 7 Gbps. It is demonstrated that the implemented transmitter can emulate 10–40”-long microstrip lines on an FR4 grade material with a peak error less than 12.5% in the pulse response.
An SRAM-based TCAM (SbT) memory architecture is proposed which exploits the tradeoffs among critical design parameters – such as throughput (T), latency (L), SRAM utilization (U), and power dissipation (P). An 18 kb TCAM is implemented on FPGA that can be adapted as latency & throughput efficient (LTE), Mid-efficient (ME), or a power & memory efficient (PME). Our implementation results show that LTE utilizes 79.3% and 96.5% more SRAM bit resources, consumes 45% and 55% more dynamic power than the ME and the PME, respectively. However, the LTE architecture shows an efficient single clock cycle latency and higher throughput than ME and PME, respectively.
Physically unclonable function (PUF) is a widely used hardware-level identification method. SRAM PUFs are the most well-known PUF topology, but they typically suffer from low reproducibility due to non-deterministic behaviors and noise during power-up process. In this work, we propose two power-up control techniques that effectively improve reproducibility of the SRAM PUFs. The techniques reduce undesirable bit flipping during evaluation by controlling either evaluation region or power supply ramp-up speed. Measurement results from the 180 nm test chip confirm that native unstable bits (NUBs) are reduced by 54.87% and bit error rate (BER) decreases by 55.05% while reproducibility increases by 2.2×.
This paper presents a pulse-based radar with ultra-wideband voltage controlled oscillator for vital-sign application. A series of digital-assisted duty-cycled probing pulses with frequency hopping technique is proposed to mitigate unwanted narrowband interferences, thereby increasing overall system signal-to-noise ratio and then enabling high resolution detection. The RF generator is utilized by an on-chip VCO with the characteristic of wide-band response by digitally switching loaded capacitor array for frequency hopping. The conventional ultra-wideband channel is further divided into several sub-channels for vital-sign sensing. An impulse radio Doppler radar is implemented and integrated with the digital-assisted oscillator to detect physiological information.
This paper proposes a wireless power transmission scheme for three-degree-of-freedom motors’ applications in the field of bionics. In order to overcome the inconvenience of the rotating device with its charged wires, the wireless power transmission of the internal image visual acquisition device is realized. A three-coil receive structure suitable for motion device is designed. Using multi-physical simulation method, the parameters, magnetic flux and received power of single-coil receive structure and three-coil receive structure for wireless power transmission are calculated. The advantages of the three-coil receive structure are obtained. Finally, the accuracy and validity of the simulation are verified by experiments.
Optical networks on chip (ONoC) delivers a promising alternative to meet growing needs of higher bandwidth and low power consumption in manycore processors. Optical routers are the key element in ONoCs that significantly affect the performance of overall network. In this letter, we propose a rearrangeable non-blocking 6 × 6 router (RoR) constructed with 2 × 2 hybrid photonic-plasmonic switching (HPPS) elements. Router architectures with 15 HPPS elements and an optimized design using reduced HPPS elements are presented and analyzed. In optimized form, proposed design consumes only 12 HPPS elements which results in low insertion loss and crosstalk noise in comparison to the un-optimized architecture. We observe up to 50% reduction in switching elements count in comparison to other router architecture of same radix.