A millimetre-wave 6-bit attenuator with high accuracy and low insertion loss by 0.15 µm GaAs PHEMT process is presented. A proposed structure is adopted to enhance the attenuation accuracy. A cascade structure is proposed to enhance isolation and compensate the insertion loss. The measurement results show that it has 0.5 dB resolution and 31.5 dB attenuation rage while the return loss is better than −10 dB for all states. The attenuation accuracy is better than 0.5 dB while the RMS attenuation error is less than 0.21 dB. The insertion loss is less than 5.7 dB while the insertion phase shift is less than −6.0°.
An idling scheme of Synchronous Switch Harvesting on Inductor (SSHI) is proposed for piling up output voltage of the piezoelectric energy (PE) harvester cycle by cycle, to deal with the PE harvester’s low output voltage. The proposed rectifier integrates active diodes and a parallel-SSHI technique with a simple control scheme, and therefore has a high efficiency. The simulation results demonstrate the feasibility of proposed rectifier, which is able to extract energy from a ultra-low-voltage PE harvester.
The mechanism and characteristic of current oscillation of four-quadrant converter with predictive current controller caused by nonlinear characteristic of the system is analyzed in the paper. With the discrete model considering the digital control delay of the single-phase four-quadrant converter, the stability condition is derived. Using the describing function of saturation characteristic, the frequency and amplitude of the nonlinear oscillation is obtained. The simulation and experiment results verify the analyses.
Interleaved switching converters are used in several applications such as power source for a PC microprocessor, one of their advantages is the capability to cancel a portion of the current ripple generated by the switching action, in the output for a buck case and in the input for a boost case. Depending to the voltage gain the operate, that current ripple can be equal to zero. Interleaving connections are made with converters of the same topology, this work explores the interleaving connection of unequal topologies Boost and Cuk, the objective is to develop an interleaving boost topology to reduce the total harmonic distortion at the input current in the full operating range, the input current ripple represents the power quality of switching mode power supplies from the input source point of view. The combined converter achieves a larger voltage gain compared with the traditional boost converter but their main advantage is the extra degree of freedom on reducing the input current ripple for certain operating conditions. Experimental results are provided to verify the theoretical analysis and prof the principle of operation.
We propose novel silicon-based surface-normal optical modulator using electro-optic (EO) polymer. The EO polymer is embedded inside a thin silicon subwavelength grating layer, which is used as both the interdigitated electrodes for effective poling of the EO polymer, and as high-Q resonant structure for the incident light to enable efficient modulation. We numerically demonstrate 10-dB intensity modulation at 1550-nm wavelength under a refractive index change of only 3.8 × 10−4, corresponding to the driving voltage below 1 V. Total-reflectance phase modulator is also demonstrated by adding a backside reflector. With inherently high-speed response over several tens of GHz, scalability to dense 2-D array integrated with CMOS driver circuitry, and relatively easy and low-cost fabrication without epitaxial process, the proposed device may find versatile applications in optical interconnects, free-space optical communications, imaging and sensing.
The contribution of alpha particles to soft error rate is quite significant, especially in planar CMOS technology. Due to high packaging density and heat dissipation mitigation technique, microelectronic devices are packaged upside down, which precludes their testing against alpha particles. The ions emitted by alpha isotopes can penetrate neither package nor substrate, from top or backside of the device, respectively, to induce upsets. This paper assesses SRAM single-event upset (SEU) sensitivity against alpha particles using high energies, irradiated from the backside of substrate. The SEU cross-section is measured at alpha various LETs (Linear Energy Transfer) values at the sensitive volume — including the Bragg’s peak, for which the sensitivity is maximum. In addition, some insights into high energy alpha backside irradiation are also discussed.
Circular metal-oxide-semiconductor field-effect transistors (MOSFETs) with various gate dimensions are fabricated on 4° off-axis and regular (100) silicon substrates. The influences of substrate orientation, gate length and width on the dc performance of the MOSFETs are investigated and the underlying mechanism is discussed. The on/off ratio, threshold voltage, field effect mobility, transconductance and drain current are compared and the differences can be explained by the interface state density and the surface roughness scattering. The results provide guidelines for the optimization and reliability of the MOSFETs on the off-axis silicon wafers.
This paper proposes a process, voltage, temperature (PVT) independent Schmitt trigger with fully adjustable hysteresis threshold voltages. These characteristics are attributed to the proposition of a self-tuning circuit in the inverter-comparator, along with a feedback controlling network for hysteresis characteristic. The proposed Schmitt trigger is designed and fabricated with SMIC 0.13 µm CMOS technology. It has much less power consumption of only 2.51 µW, and features also an adjustable hysteresis threshold voltages ranging from 350 mV to 850 mV at a minimum supply voltage of 1.0 V. All these advantages make it very suitable to work as 1-bit digitization in a low power sensing node.
Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.
Optical routers constructed by waveguides and microring resonators (MRs) play an important role for realizing non-blocking multicast-supported communication of Optical Networks-on-Chip (ONoCs). Most of the prior methods use building blocks to construct optical routers that cannot support multicast communication. Some prior optical routers support multicast communication by using large number of MRs with low utilization. In this letter, a universal method for designing non-blocking multicast-supported optical routers is proposed. Given the topology of the router that satisfies some conditions, this proposed method leverages broadband MRs and perform recursion pruning algorithm to obtain a multicast-supported router design with fewer MRs and high utilization. Based on this method, a five-port non-blocking multicast-supported optical router is designed. It saves up to 73.3% MRs and enhances 100% of the utilization compared with previous reported five-port routers.
The modulated wideband converter (MWC) is a powerful sub-Nyquist sampling system, which can acquire sparse wideband analog signal without prior information of frequency support. In this letter, we aim at enlarging the input bandwidth of MWC under a certain chip rate constraint, which is realized by utilizing run length limited (RLL) sequence in the modulation stage. Simulation results show that when applying our method, input bandwidth of MWC can be improved by 25% without reconstruction performance loss.
Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65 nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).
A three-dimensional power segmented tracking for adaptive digital pre-distortion is presented to stabilize the linearization of radio frequency power amplifiers (PAs). It contains long term average power segmented dimensional, short term average power segmented dimensional and instant power segmented dimensional that can correct and track the various nonlinear characteristics of PAs. Moreover, a constraint least square algorithm by indirectly learning structure is employed to initial the parameters and a least mean square algorithm by directly learning structure is used to adaptive calculate the parameters. Experimental results show that the proposed method has stable improvements in comparison with previous methods.
A borehole electromagnetic induction (EMI) system with noise cancelation for casing inspection is presented. Based on the analysis of the model for received signal in multi-cylindrical borehole structures, we choose to utilize a receive-only channel as the reference to cancel the effect of the background noise, where a registration matrix is used to compensate for the correlation of the non-isolated reference channel. Moreover, the performance of noise cancelation is verified by applying it to an oil borehole EMI system for the inspection of oil-well casings. Field experiments are conducted and the results demonstrate the effectiveness of the proposed method.
This paper presents a novel forced-resonance microwave technique to detect surface cracks in metal. This technique utilizes a cutoff cavity with a control element and a voltmeter to probe for surface cracks in the metal. Crack signals are detected by using forced resonance from the cutoff cavity probe. In the absence of a crack, the cutoff cavity probe aperture with a shorting plate (short-circuit) can resonate forcefully by adjusting the control element, and the forced resonance characteristics of the cutoff cavity are then probed by a detector (voltmeter) with voltage maximized. However, in the presence of a crack, the forced-resonance cutoff cavity probe aperture, in turn, changes the resonance properties from a short circuit, and the resonance variations are then detected by the detector as the voltage varies. The validity of this method was established by comparing experimental results with theoretical values.
In this paper a hybrid optimization synthesis method is presented for arbitrary mixed topology microwave filter (i.e., part of the structure with an extracted-pole and part with cross-coupled configurations). Compared with the conventional synthesis method for mixed topology filter, the method presented in this paper has following advantages: 1. There is no rotations for coupling matrix. 2. The method is suitable for terminal extracted-pole sections and inside extracted-pole sections. 3. It is no need to care the extra phases for the characteristic polynomials. This method consists of a genetic algorithm (GA) for a global optimizer and Solvopt for a local optimizer, respectively. Four examples are given for illustrating the proposed techniques for the synthesis of mixed-topology prototype filters. Excellent agreement between the response computed from characteristic polynomials and the response computed from couplings is obtained from the proposed method.
A novel two-way power divider (PD) with wideband frequency response is presented in the paper. By combining a Gysel and a modified Wilkinson power divider, the proposed PD achieves a balance between heat-handling and bandwidth. Owing to its symmetrical structure, the operating mechanism can be derived by the even- and odd-mode analysis. Then, a prototype of an in-phase power divider operating at 3.75 GHz has been designed, fabricated and measured. The measured results demonstrate an acceptable bandwidth of about 72% with isolation >15 dB and return loss >14 dB.
A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system’s standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz).