Homodyne optical phase-locked loop (OPLL) is one kind of PLLs applied in optical field to achieve phase locking between two optical signals. Although there are already some software emulation and s-domain modeling methods studied for homodyne OPLL, few studies about z-domain model of OPLL are reported. For homodyne digital OPLL(DOPLL), the performance of homodyne DOPLL can be analyzed more accurately by z-domain model. So a z-domain modeling methodology for homodyne DOPLL is proposed in the letter. In the proposed methodology, optical related components and analog to digital converter (ADC) are treated as one group. Then with formula transformation, z-domain model for homodyne OPLL is built successfully. Finally, a case study is given, several simulations by z-domain model and Simulink behavioral model are made with the same design parameters. These simulation results agree very well and verify the correctness of z-domain model.
Hardware trojans(HT) is one of the main threats for hardware security, especially attacks on General-Purpose Registers(GPRs) of processors. This paper presented a novel method to detect HT induced attacks by comparing the states of GPRs with an embedded reference model in real time. Firstly, the instruction sequence was realigned with four principles. Secondly, based on the realigned instruction stream, a reference model for GPRs was built. Finally, HT induced attacks on GPRs can be detected by comparing the expected GPRs’ state from the reference model with the sampled GPRs’ state from processors. We integrated this method into a RISC-V core of PULpino and investigated the feasibility with different programs. The experimental results showed that all the randomly inserted HT attacks can be detected in real time with the latency of two clock cycles.
A low phase noise quadrature LO-generator for dual-band wireless local area network (WLAN) applications is presented. The quadrature LO-generator is composed of a clock receiver, a CML divider, and two quadrature dividers for the dual-band, respectively. A clock receiver converts the single-ended clock to a differential signal. Then a quadrature divider with a 25% duty cycle generates four quadrature signals for mixers. The split-grounded architecture and multiply ground pads decrease the inductive component of ground impedance as well as the ground bounce of the single-ended input. The phase noise is -143dBc/Hz and -149dBc/Hz at 1MHz offset in the 2.4-GHz and 5-GHz bands, respectively.
This paper presents an algorithm-hardware co-design of ultra-high radix modular multiplier for high throughput modular multiplication. First, to speed up the modular multiplication, we exploit an ultra-high radix interleaved modular multiplication algorithm with a novel segmented reduction method, which reduces the number of iterations and pre-computations. Then, to further improve the throughput of the modular multiplication, we design a highly parallel modular multiplier architecture. Finally, we implement and verify the modular multiplier using the Xilinx Virtex-7 FPGA. Experimental results show it can perform a 256-bit modular multiplication in 0.56 µs with the throughput rate of up to 4999.7 Mbps.
This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm2. By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.
This paper presents a 79 GHz low noise amplifier (LNA) design featuring high gain fabricated in a 40-nm CMOS process. To make better use of active devices, we propose an inductor-embedded neutralization technique. The implemented prototype consists of four-stage common-source amplifiers using the proposed technique and transformer-based matching networks. The measurement results show that the amplifier realizes a peak gain of 23dB at 79GHz with 14.4mW power dissipation and 0.4mm2 area occupation. The LNA achieves a minimum noise figure (NF) of 6.3dB.
A reconfigurable bandstop microstrip line filter with wide continuously adjustable stopband is proposed in this letter. Dumbbell-shaped defected ground structure cells based on dual coupling slots are used to reduce the complexity of the filter and simplify the equivalent circuit modeling. Three varactors crossing the center coupling slots are utilized together with isolating capacitors to obtain the reconfigurability, of which the frequency range can be adjusted from 1.8 to 8.0 GHz. An equivalent-circuit model using coupled LC resonators is developed to firstly attain physical understanding of the filter’s working principle and secondly to assist the filter design. Three pairs of perpendicular stubs are introduced onto the microstrip line to improve the transmission and maintain signal integrity in the passband. The filter has been fabricated and experimentally characterized, with the good agreement observed between simulation and measurement validating the concept.
Piecewise quadratic polynomial approximation is a well-established hardware function evaluation technique. In this paper, we demonstrate the analysis and optimization of hardware implementation of sine and cosine through piecewise quadratic polynomial for single-precision floating-point operations. First, detailed approximation error analysis was used to rapidly obtain the non-uniform segmentation and guarantee faithful rounding. Second, theoretical analysis demonstrates that the monotonicity of the algorithm using segmentation is consistent with the original sine and cosine function. Moreover, the bit-width is optimized for the sine and cosine floating-point arithmetic units based on static analysis and dynamic monitoring to reduce the hardware cost. Experimental results show that the implementation for sine and cosine functions meets the requirements of faithful rounding and monotonicity with reasonable hardware cost.
A low-phase-noise 25-GHz quadrature voltage-controlled oscillator (VCO) using 180-nm TSMC CMOS is presented. To equalize the oscillation frequency to the LC-resonant frequency, a phase shifter at a transistor gate adjusts a phase delay due to an RC delay in a transistor. This phase-adjusting architecture extends operation bias range and suppresses phase noise by 6 to 9 dB compared with a conventional differential VCO.
This paper presents a black-sun immune correlated double sampling (CDS) scheme for high-quality imaging. Based on an analysis of signal characteristics in strong light conditions, a clamping circuit-based signal difference generator is proposed to accurately present the bright light information. The proposed scheme eliminates the black-sun noise with simple circuitry to improve the A/D conversion efficiency. Moreover, it can be is reversible to the conventional algorithm so that it still preserves the structural advantages of the existing CMOS image sensor (CIS) structure. A prototype CIS with a column-parallel 11-bit single-slope (SS) analog-to-digital converter (ADC) was fabricated in a 0.11-µm 1P4M CIS process with a 2.9-µm pixel pitch.
We propose a 3dB polarization coupler in which the input light of the TE mode is converted into two out-of-phase TM modes, and the input light of the TM mode is split into two in-phase TM modes. This was designed with a 3-steps taper structure. When a Mach-Zehnder interferometer (MZI) is composed of the proposed 3dB coupler, the polarization of the output light is rotated depending on the phase difference between the two arms. By incorporating optical phase shifters, polarization rotation can be controlled in MZ devices. In this study, we optimized the design of the proposed 3dB coupler, and numerically demonstrated polarization rotation in an MZI with the proposed couplers, depending on the phase difference between the two arms.