A low power dynamic-distributing-bias CMOS temperature sensor is presented for temperature-sensing RFID tag. To reduce the chip area and power consumption, we propose a new hybrid PTAT/REF current generator. A new current-mode readout scheme is devised, which is dedicated to improve the dynamic range utilization of ADC and further reduce the power consumption. Fabricated in 0.153µm CMOS process, the sensor shows a measured inaccuracy of -0.6°C to +0.8°C from -40°C to 125°C. This performance is obtained by using precision and nonlinearity compensation techniques such as V_BE trimming, ratio-metric curvature correction, chopping and dynamic element matching (DEM). The sensor has low power consumption of 2.21µW under a 1.6V supply and occupies an area of 0.07mm².

Heterogeneous systems with CPU and GPU cores integrated on a single chip provide fast communication between CPU and GPU cores and high performance. The last-level cache (LLC) is one of the most essential shared memory resources in heterogeneous CPU-GPU systems. Due to the different LLC access behaviors and collaboration patterns from CPU and GPU, the shared LLC is not guaranteed to be used efficiently without any management. In this paper, we propose a reuse distance-based LLC management mechanism to improve system performance and save energy consumption. Our mechanism monitors reuse distances of cache lines accessed by CPU and GPU in sampling cache sets. It compares average reuse distance values of CPU and GPU cores to determine cache line insertion, promotion, and eviction in the LLC. Our mechanism can achieve significant performance improvement with a higher LLC hit rate. The evaluation results show that our management method can improve performance by up to 16% and 7%, and achieve LLC energy savings of up to 13% and 4% over the LRU and TAP-RRIP policies, respectively.

A monolithic single-pole, fourteen-throw (SP14T) antenna switch module (ASM) with on-chip transmit filters is implemented in a 180nm silicon-on-insulator CMOS process for multi-mode multi-band cellular handsets. To ensure compatibility with control interfaces and multi-band linear operation, a mobile industry processor interface decoder, a positive voltage regulator, a negative voltage generator, and an asymmetric RF-core topology are incorporated. Moreover, an optimal on-chip filter matching method is introduced to achieve a fully integrated solution that enhances both harmonic performance and miniaturization. The SP14T ASM exhibits excellent insertion loss, isolation, linearity, and harmonic performance across different modes.

The ResNet series of networks has demonstrated powerful capabilities in the fields of object detection and image classification, garnering increasing attention from researchers. However, due to their deep network architectures, accelerator development based on FPGA faces challenges associated with limited on-chip resources and lengthy design cycles. This paper presents a versatile hardware acceleration system based on FPGA, achieving optimization through both hardware implementation and software inference architecture. The system reduces network complexity by employing techniques such as inter-layer fusion and dynamic quantization, while enhancing hardware resource utilization through channel parallelism and tightly-pipelined hardware design principles. By configuring and reusing computation units, the forward inference process of ResNet series networks can be rapidly deployed on FPGA, shortening the development and validation cycles. The proposed system is validated using the ResNet-18 model on a PYNQ-Z2 development board within a gesture recognition application scenario. The overall power consumption of the system is 2.136W, with hardware inference accuracy reaching 98.87%.

This paper presents a technique for designing broadband reconfigurable power amplifier matching networks using equal Q values. The precise values of the matching elements are determined while also considering restrictions on the impedance transformation ratio and Q value. To achieve the desired band reconfigurability, we leverage the distinct characteristics of the devices at different frequencies and wavelengths to create an equal Q matching network and subsequently calculate the second band. An ultra-wideband reconfigurable RF power amplifier is created to test the viability of the suggested design approach. The test results show that the output power of the amplifier is 51.8-52.5dBm and the drain efficiency is 45%-62% in the frequency ranges of 170-400MHz and 470-860MHz. In addition, the linearity test results of the circuit using a two-tone signal with a frequency interval of 0.1MHz show that the IMD3 value of the whole bandwidth is lower than -20dBc at an output power of 47dBm.

This paper introduces an innovative design for double-transverse-coupled-cavity (DTCC) VCSELs aimed at achieving high-speed modulations exceeding 21GHz with single mode operations. The lateral in-plane optical feedback across both cavities facilitates a significant enhancement in direct modulation bandwidths. Open eye diagrams were discerned for data rates as high as 36Gbps (NRZ) and 48Gbps (PAM4).

A high efficiency rectifying circuit with multi-section impedance conversion and harmonic suppression is proposed. A shorted stub is used to compensate the rectifying diode capacitive impedance. Furthermore, a matching filter network is integrated at the DC output port to eliminate the fundamental and high order harmonics which are generated by the diode nonlinearity. The above efforts could effectively improve the conversion efficiency of rectifying circuit. A wireless RF power transmission experiment is implemented, the output voltage is 2.003V with the distance between the transmitting and receiving antenna is1 m. The output voltage is linear with the transmission distance, and the maximum output voltage can reach 3.17V. Experimental results show that the proposed rectifying circuit achieves high rectifying efficiency of 59.6% at 5.8GHz.