In this paper, an improved sliding mode observer (SMO) is proposed to guarantee the position detection accuracy of the permanent magnet synchronous motor (PMSM) developed for magnetic suspension molecular pumps (MSMP). Since the traditional SMO based sensorless scheme has chattering problems, and considering the existence of harmonics component, the estimated back-EMF waves should be further processed. For this reason, a novel back-EMF observer is proposed to extract the fundamental wave of the estimated back-EMF signals. Experimental results show the effectiveness of the proposed sensorless control of PMSM.
In this paper, a modified microstrip slot aperture feed is introduced which generates TEσ13 modes in a cubic dielectric resonator antenna resulting in a high gain (simulated = 10.5 dB and measured = 9 dB). The proposed feed can be realized by replacing the rectangular stub of microstrip slot aperture feed with a circular metallic stub of radius 3 mm. The proposed feed excites the dielectric resonator antenna around a resonant frequency of 5.78 GHz covering 5.725–5.850 GHz WIFI band. The antenna exhibits an impedance bandwidth of 130.2 MHz, and 135 MHz in simulations and measurements respectively, and a stable gain throughout the 5.78 GHz WIFI band with a maximum of 9 dB in measurements.
The bandwidth demands from mobile application processors (APs) have been consistently growing to run multiple compute- and memory-intensive workloads concurrently. The Low-Power Double-Data Rate (LPDDR) DRAM family has been the de-facto standard for main memory, whose operating frequency has been scaled up to meet these demands. However, frequency scaling poses many design challenges due to limited power budget, timing, and power/signal integrity issues. JEDEC has recently released the WideIO2 DRAM standard to provide high bandwidth at a low frequency. However, WideIO2 DRAM cannot completely replace LPDDR devices because it cannot provide enough capacity and bandwidth by itself. Thus, this paper proposes a heterogeneous mobile memory system (HMMS) using both types of DRAM devices. HMMS employs an efficient page migration scheme to serve more requests from energy-efficient WideIO2 DRAM devices. HMMS uses a small on-chip page location table at each DRAM controller to track page remappings without requiring a master table in off-chip DRAM. To minimize bandwidth and energy wastes from excessive page migrations, HMMS selects strong hot pages for migration, adjusts the page migration threshold dynamically and employs a migration stop mechanism. Our evaluation using 10 multi-programmed workloads demonstrates that HMMS improves the performance and energy-delay product (EDP) by 13% and 21%, respectively, over the baseline heterogeneous memory system with no migrations.
This paper presents a novel design of frequency selective surface (FSS) with band-stop characteristics at dual frequency bands. The FSS element is a hybrid set consisting of four meander lines square loops and a criss-cross element, and can be implemented on a single-layer PCB substrate at low cost. It is found that the band-stop characteristics are valid for a relatively wide angular range of field incidence. Furthermore, structural parameters have been identified for the adjustment of flexible band separation. In this work, an equivalent circuit model is further developed to illustrate the electrical properties of band-stop as a space filter. The concept has been validated by considering a prototype at 6.3 and 8 GHz, where the simulation and measurement frequency responses are compared to exhibit the transmission characteristics of this FSS design.
The rapid growth in microprocessor’s performance increases the power consumption significantly, resulting in rising microprocessor and system temperatures. High temperatures and eminent thermal variations of processors create severe challenges in system reliability, and cooling costs. Therefore, power and thermal management have become prominent issues of portable computer systems. Dynamic threshold hopping and supply voltage scaling (DTSVS) is an effective low-power design technique for reducing dissipated power. The technique adjusts the body bias (VBB) or threshold voltage (Vth) and, correspondingly, the supply voltage (Vdd) adaptively in order to obtain a minimum power consumption and extend the processor’s lifetime on a revolutionary scale. In this study, the optimal simultaneous combination set of the threshold and supply voltage (Vth-Vdd) scaling is proposed to reduce power dissipation in the core of high-performance portable processors. Analysis and SPICE simulations are used to evaluate the presented theoretical basics and fundamentals. To ensure optimal Vth-Vdd sets; Particle Swarm Optimization (PSO) algorithm and Pareto Front (PF) solution are used. Both theoretical and simulation results show that, optimal amount of power consumption reduction has been obtained for different temperatures and workload environments.
A polarization dependent, left handed metamaterial based on single layer patterned resonant structure intended for C- frequency band with 2.14 GHz wide bandwidth is proposed. The size of a single unit cell is 11 × 11 mm2 and the effective medium ratio is 5.27. CST Microwave Studio electromagnetic simulator is used to design and numerical analysis as well as Agilent N5227A VNA is for measurement. The measured results show resonance peaks at 5.17 GHz and applicable for IEEE 802.11a Wi-Fi and cordless telephone applications. The proposed metamaterial is explained by lumped circuit model and exhibits left handed characteristics at 6.43 GHz.
In view of the high demand for low-power biomedical signal-processing schemes occupying very less on-chip areas, we propose a low-power highly integrated system-on-chip (SoC) design comprising a nonuniform biomedical sensing signal conditioning circuit and a 32-bit microprocessor. The proposed design is implemented using a 0.18 µm CMOS EFLASH process in an area of 4.2 mm2, and is applied in PPG, ECG and BP measurements. Experimental results show that our SoC design provides extremely good performances for sparse features of all three biomedical applications. The charge consumption is 25 mAh for three months, for an experimental board design including sleep current and junction leakage current.
In this letter, a compact and high isolation balanced-to-balanced microstrip diplexer with mixed coupling is proposed via the combination of two high selectivity and common-mode (CM) suppression balanced bandpass filters (BPFs) without extra junction matching network. The single-ended mixed coupling BPFs are composed of two short-ended stepped impedance resonators (SIRs). The mixed coupling is modeled in a way that both magnitudes and phase differences of constituted capacitive and inductive couplings are made use of in filter synthesis. Multiple transmission zeros (TZs) can be generated by the different electric and magnetic coupling coefficients ratios and electric length ratios. Furthermore, the loading effect of a balanced filter on another balanced filter can also generate a new differential-mode (DM) TZ at the other passband to improve the isolation. Finally, the proposed diplexer for WLAN (wireless local area networks) application is fabricated and measured. The simulated and measured results exhibit a satisfactory agreement to validate the proposed configuration.
In this paper, we propose a D-band switch design using a parallel-stripline swap hybrid coupler with defected ground structure (DGS). Compared to the conventional transmission line (TL) with high insertion loss at high frequency, the equivalent capacitance introduced by the coupler gap leads to series resonance condition which results in lower insertion loss at the higher frequency. The hybrid coupler enables two additional degrees of design freedom since the capacitance and inductance can be tuned by the structural dimension of the coupler. The fabricated switch with core area of 0.0036 mm2 shows measured insertion loss of 1.6–3 dB from 110–134 GHz, return loss of higher than 10 dB and isolation level around 16 dB.
A wideband high-efficiency V-band CMOS power amplifier (PA) is proposed in this paper. Neutralization technique is used to reduce the Miller effect and improve the power gain. A wideband on-chip transformer is used to adjust the transistors’ voltage waveform to improve the PAE performance. The PA works from 51 GHz to 64 GHz with 13 GHz absolute bandwidth and 22.6% relative bandwidth. The output power reaches 14.9 dBm with 16.3% peak PAE. The circuit is designed in a 65 nm CMOS technology.
To recover the errors occurred in flash-based storage, well-known error correction codes (ECC) are integrated into flash memory controller. However, the existing error correction codes have their inherent limits to recover more error than they recover, so more additional schemes should be considered for the higher reliable flash storage systems. In this paper, we investigate duplicated data management to enhance data reliability as replication. To minimize space overhead of the duplication management, we consider two issues, minimizing fingerprint length and enlarging hash chunk size of duplication checking. At most cases, the proposed duplication management scheme can have better reliability than adding more ECC parity bits in the aspect of space overhead.