An ISM-band CMOS OOK receiver is presented as a possible wake-up receiver for implantable cardioverter telemtry system applications. It is based on the heterodyne architecture with uncertain IF. Current reuse technique is employed such that the LC VCO current is reused by the rest part of OOK receiver circuitry. Fabricated in 0.18µm CMOS, the receiver dissipates 1mW from 1.8-V supply. Test results show that the current-reuse OOK receiver is fully functional and meet the performance requirements. The proposed circuit structure can be effective for low-power OOK wake-up receiver design in implantable telemetry devices.

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The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dual-port memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.

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The inductive degenerated Common Source (CS) Low Noise Amplifier (LNA) is one of the widely used topology for realizing narrow band Radio Frequency (RF) CMOS LNAs. Though this scheme has been in use for a long time, realizing an optimum design still remains a challenging task. The present paper reports a simple and direct design space exploration procedure for the inductive degenerated CS LNA. The procedure first involves the use of a circuit simulator (Cadence Spectre) to generate a Look Up Table of small signal parameters. These are then used in a numerical simulator (MATLAB) to explore the entire design space by computing the various performance parameters and arrive at the final optimal designs. The predicted performances of the optimum designs were then verified using UMC 180nm CMOS process parameters in Cadence Spectre. Completing all the computations on a typical low end desktop system within about an hour, the results presented indicate that one can search a design space of nearly fourteen million design candidates and arrive at an optimum of one’s choice.

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A fast-locking fractional-N frequency synthesizer with a fourth-order PLL is presented for a receiver of multiple positioning systems. In order to reduce the locking time a new method of only performing LPF structure transformation is proposed, which exploits the large bandwidth without changing the charge-pump current during the transient state. The bandwidth of the third-order PLL with the second-order LPF during transient state is 10 times larger than that of the fourth-order PLL in the phase-locked state. Furthermore, a pre-charging circuit and the unchanged charge-pump current can significantly accelerate the phase locking. Simulation results show that the longest locking time is less than 10µs in seven modes of three positioning systems (GPS, Galileo and Beidou). For each mode, the in-band and out-of-band phase noises are no larger than -93dBc/Hz and -118.5 dBc/Hz, respectively, and the spurs are less than -56.4dBc at 8.043MHz offset frequency. Total power consumption is 15.21 mW under 1.8V supply.

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A novel variable gain amplifier for broadband application is proposed with a tapered traveling wave matching network, an output RC network and a cascode gain stage. The traveling wave matching network and RC network lessens input and output return loss dependence on VGA’s gain which is adjusted by biasing of the gain control circuit respectively. The proposed wide band (DC-12GHz) VGA is implemented in 2µm InGaP/GaAs HBT (f_T of 29.5GHz) technology with die size of 1×2mm². As gain control voltage sweeps, the VGA shows a gain tuned from −15dB to 15dB, while S11 (lower than −15dB) and S22 (lower than −10dB) almost unchanged over the operation frequency band.

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This paper presents a new fully-digital high-frequency (HF) backscatter radar system for oceanographical remote sensing. The fully-digital receiver is designed that employs directly radio freqency (RF) sampling, digital down-conversion, and digital pulse compression techniques. The difference between this system and ordinary analogue system is illustrated. Results of closed-loop test and field experiment conducted on the coast of the Eastern China Sea are given to prove good performance of the system.

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The through silicon via (TSV) technology provides a promising option to realize three dimensional (3D) gigscale systems with high performance. As the fundamental elements in this system, Redistribution Layers (RDLs), TSVs, and bumps, which constitute a TSV channel together, transmit high speed signals. Consequently the impedance mismatch among these elements causes signal reflection along the channel that need to be investigated. Chebyshev Multisection Matching Transformers are proposed to reduce the signal reflection of the TSV channel when operating frequency up to 20GHz, by utilizing of which S₁₁ and S₂₁ has been improved of 150% and 73.3%, respectively.

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Process variations yield the asymmetry on core performance in many-core processors. Adaptive voltage scaling can hide the variations, but that results in the different thermal characteristics of cores. By using the thermal characteristics, the efficiency of energy optimization and temperature management can be improved. Experiments showed that the proposed dynamic voltage frequency scaling consumes up to 25.2% less energy than the existing thermal management technique while remaining the ratio of peak temperature violations under 1%.

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The traversal process in accelerated ray tracing algorithms requires many memory transactions of an acceleration structure. We present a pre-fetching system to pre-load potential node data into a cache. Experimental results show that the proposed scheme increases the performance of a cache system by reducing the cache miss rate.

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It is well known that the rate of convergence of the Krylov Subspace Methods (KSMs) applied to the solution of the linear systems of equations arising from the discretization process of the E-Field Integral Equation (EFIE) by Method of Moments (MoM), can be improved by a suitable preconditioning strategy. In this paper, we analyze the performances of an easy preconditioner based on the skew-Hermitian part X of the impedance matrix Z. Numerical examples illustrate its performances and validate the proposed approach.

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