This article presents a novel broadband H-plane rectangular waveguide T-junction structure for unequal power dividers at Ka-band. Inspired by H-plane waveguide bend structure and directional coupler, T-junctions with high power splitting ratio are invented. Compared with the conventional T-junction structures, their bandwidths are obviously broadened. Two in-phase power dividers at Ka-band with different power division ratios (1:4 and 1:8) are designed and fabricated to verify the practicability of the proposed structure. The measured results agree well with the simulations and the broadband characteristics are obtained. The bandwidth of unequal power divider is 44.06% for the 1:4 power divider and 38.9% for the 1:8 power divider, respectively.

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A simple first order allpass filter (APF) realization scheme with single current feedback amplifier (CFA) is presented; the phase-select component Y (= sC) is grounded. Analysis indicates that effects of imperfect port mismatch ratio of the CFA are quite insignificant. However the device parasitic capacitors introduce certain phase error at relatively higher frequencies. This simple circuit may be extended to second order APF design, if desired with Y as a shunt −LC resonator; L being a lossless inductor simulated by a DVCCTA element. Literature study on recent first order APF indicates that these are based on active elements that are based essentially on assorted conjoined versions of two types of devices.

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Storage Class Memory (SCM) emerges as a potential technology because of its byte-addressability and non-volatility. However, existing file systems are not efficient for SCM because they are optimized for hard disks devices. In this paper, we propose a new file system called random access file system (RAFS), which is implemented on Linux as a prototype. In RAFS, we simplify system architecture and adopt memory mapping and XIP mechanisms to improve performance. We have analyzed and evaluated its performance with multiple workloads. Results show that RAFS outperforms Ext4 under the same condition, especially for random access scenarios.

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Stepped impedance resonators (SIRs) are composed of multiple transmission lines having different characteristic impedances, and can control higher-order mode resonance frequencies. Here, by using these properties, identification codes from a resonator were systematically generated by introducing symmetric multimode SIRs composed of same-length transmission lines. In the other direction, resonator codes were identified by detecting their higher-order mode resonance frequencies. This paper describes these resonance properties and experimental results from multimode SIRs, and discusses their applicability in chipless RFID tags.

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In this paper a new topology of high step-down dc-dc converter is proposed. The proposed converter uses an interleaved structure with one phase using a traditional buck converter and the second phase uses its inverted version. By this technique a high step down voltage conversion can be achieved as compared to the traditional interleaved buck converter. Operating principle and steady state analysis of proposed converter is given. An experiment is carried out on a 25 V input, 5 V/1 A output laboratory prototype to obtain experimental results and verify the effectiveness of the proposed converter. An efficiency of 83.7% is achieved at the rated load and a maximum efficiency of 88% is achieved at 0.5 A load current.

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Modern data appliances face severe bandwidth bottlenecks when transferring data between storage and host. In this paper, we present a storage system which can improve performance more than three times by using an FPGA to implement the off-load engine. Regardless of the data size, the host CPU utilization varies vastly between the two systems, traditional way uses 100% and the system presented only uses 1%. Compared to the traditional way, the memory allocation has been greatly reduced. The system presented is explored for emerging NVRAMs which have many benefits compared to the traditional memory.

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This paper presents a novel compact in-line triplet substrate integrated waveguide (SIW) bandpass filter. The filter is composed of two SIW cavity resonators and an etched one-half wavelength grounded coplanar waveguide (GCPW) line resonator. The GCPW line resonator is etched between two SIW cavity resonators to obtain more compact size. A transmission zero on the upper stopband is created by the cross coupling, which allows the filter implementation in in-line with sharp upper cut-off skirts. Finally, a compact third-order 15 dB return loss filter with a fractional bandwidth (FBW) of 7% at 5.5 GHz is designed, fabricated and measured. The experimental results show good agreement between the simulated and measured results.

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In this paper, an efficient architecture of an FPGA-based bitmap index creation is proposed. The design utilizes a content addressable memory together with a bit-level transpose matrix to index multi-record documents by several given keywords. The experiments in a Cyclone V SX FPGA proved that our circuit could attain throughput of 330.6 million records per second while only using around 71% of embedded memory together with 45% of lookup tables and registers. In fact, achieved throughput is 2.8 times and 1.7 times as high as that of CPU-based and GPU-based design, respectively.

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A multi-beam forming method was proposed for parametric array research. It was supposed that by this method, parametric array could generate a difference frequency wave containing multiple sub-beams. In order to verify the feasibility of the method, simulation and experiments were conducted to generate a difference frequency wave containing double sub-beams. As seen from the test result, the generated difference frequency waves present a double sub-beams shape. In addition to the partial overlap that exists between the sub-beams, the experimental data matched the anticipated results well. Therefore, the proposed multi-beam forming method was proved to be effective and feasible.

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